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| document no. u17717ej2v0ud00 (2nd edition) date published november 2005 n cp(k) printed in japan preliminary user?s manual v850es/hj2 32-bit single-chip microcontrollers hardware 2005 pd70f3709 pd70f3710 pd70f3711 pd70f3712
preliminary user?s manual u17717ej2v0ud 2 [memo] preliminary user?s manual u17717ej2v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 preliminary user?s manual u17717ej2v0ud 4 minicube is a registered trademark of nec electronics corporation in japan and germany. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics products depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. ? ? ? ? ? ? ? m5d 02. 11-1 the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": preliminary user?s manual u17717ej2v0ud 5 [memo] preliminary user?s manual u17717ej2v0ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/hj2 and design application systems using the v850es/hj2. purpose this manual is intended to give users an understanding of the har dware functions of the v850es/hj2 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications (target) ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the overall func tions of the v850es/hj2 read this manual according to the contents . to find the details of a regi ster where the name is known use appendix a register index . to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. to know the electrical spec ifications of the v850es/hj2 see chapter 27 electrical specifications (target) . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defi ned as a reserved word in the device file. the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx. yyy? is described as is in a program, however, the compiler/assembler cannot recognize it correctly. preliminary user?s manual u17717ej2v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 preliminary user?s manual u17717ej2v0ud 8 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/hj2 document name document no. v850es architecture user?s manual u15943e v850es/hj2 hardware user?s manual this manual documents related to development tools document name document no. operation u17293e c language u17291e assembly language u17292e ca850 ver. 3.00 c compiler package link directives u17294e pm+ ver. 6.00 project manager u17178e id850qb ver. 3.10 integrated debugger operation u17435e sm850 ver. 2.50 system simulator operation u16218e sm850 ver. 2.00 or later system si mulator external part user open interface specification u14873e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 or later real-time os task debugger u17420e basics u13773e installation u17421e technical u13772e rx850 pro ver. 3.20 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp4 flash memory programmer u15260e preliminary user?s manual u17717ej2v0ud 9 contents chapter 1 introduction ...................................................................................................... ...........17 1.1 general ........................................................................................................................ .............17 1.2 features....................................................................................................................... .............19 1.3 application fields ............................................................................................................. ......19 1.4 ordering information ........................................................................................................... ...20 1.5 pin configuration (top view) ......................................... ........................................................21 1.6 function block configuration........................................ ........................................................23 1.6.1 internal bl ock di agram ......................................................................................................... ...... 23 1.6.2 internal units ................................................................................................................. ............. 24 chapter 2 pin funct ions.................................................................................................... ............26 2.1 pin function list .............................................................................................................. .......26 2.2 pin status ..................................................................................................................... ............33 2.3 description of pin functions ......................................... ........................................................34 2.4 pin i/o circuit types and recommended connection of unused pins ............................43 2.5 pin i/o circuits............................................................................................................... ..........46 2.6 cautions ....................................................................................................................... ............47 chapter 3 cpu function..................................................................................................... ............48 3.1 features....................................................................................................................... .............48 3.2 cpu register set............................................................................................................... ......49 3.2.1 program regi ster set ........................................................................................................... ....... 50 3.2.2 system regi ster set............................................................................................................ ........ 51 3.3 operation modes ................................................................................................................ .....57 3.3.1 specifying oper ation mode ...................................................................................................... .. 57 3.4 address space .................................................................................................................. ......58 3.4.1 cpu address space.............................................................................................................. ..... 58 3.4.2 wraparound of cpu addr ess spac e .......................................................................................... 59 3.4.3 memory map..................................................................................................................... ......... 60 3.4.4 areas .......................................................................................................................... ............... 62 3.4.5 recommended use of address s pace ....................................................................................... 66 3.4.6 peripheral i/o regist ers....................................................................................................... ....... 69 3.4.7 special r egister s .............................................................................................................. .......... 80 3.4.8 cauti ons ....................................................................................................................... ............. 84 chapter 4 port f unctions................................................................................................... .........87 4.1 features....................................................................................................................... .............87 4.2 basic configuration of ports ...................................... ...........................................................87 4.3 port functions ................................................................................................................. ........89 4.3.1 operation of port func tion ..................................................................................................... ..... 89 4.3.2 notes on setti ng port pins ..................................................................................................... ..... 90 4.3.3 port 0......................................................................................................................... ................ 91 4.3.4 port 1......................................................................................................................... ................ 97 4.3.5 port 3......................................................................................................................... .............. 101 4.3.6 port 4......................................................................................................................... .............. 108 preliminary user?s manual u17717ej2v0ud 10 4.3.7 port 5 ......................................................................................................................... ..............111 4.3.8 port 6 ......................................................................................................................... ..............117 4.3.9 port 7 ......................................................................................................................... ..............125 4.3.10 port 8 ......................................................................................................................... ..............127 4.3.11 port 9 ......................................................................................................................... ..............131 4.3.12 port 12 ........................................................................................................................ .............142 4.3.13 port cd ........................................................................................................................ ............144 4.3.14 port cm ........................................................................................................................ ...........146 4.3.15 port cs ........................................................................................................................ ............149 4.3.16 port ct ........................................................................................................................ ............152 4.3.17 port dl ........................................................................................................................ ............155 4.3.18 port pins that function alter nately as on-chip debug func tion ...................................................158 4.3.19 register settings to use port pins as alternate- function pins ....................................................159 4.4 block diagrams of port........................................................................................................ 1 66 4.5 cautions ....................................................................................................................... ......... 195 4.5.1 cautions on se tting port pins .................................................................................................. .195 chapter 5 bus control function ................................ .......................................................... 19 6 5.1 features....................................................................................................................... .......... 196 5.2 bus control pins............................................................................................................... .... 197 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed...............197 5.2.2 pin status in eac h operation mode ...........................................................................................197 5.3 memory block function....................................................................................................... 198 5.4 bus access ..................................................................................................................... ...... 199 5.4.1 number of clo cks for a ccess.................................................................................................... 199 5.4.2 bus size setti ng func tion ...................................................................................................... ....199 5.4.3 access by bus si ze ............................................................................................................. .....200 5.5 wait function .................................................................................................................. ...... 207 5.5.1 programmable wait function ....................................................................................................2 07 5.5.2 external wait func tion......................................................................................................... ......208 5.5.3 relationship between programmabl e wait and exte rnal wa it ................................................... 208 5.5.4 programmable address wait func tion .......................................................................................209 5.6 idle state insertion function ............................................................................................... 210 5.7 bus hold function.............................................................................................................. .. 211 5.7.1 functional outlin e............................................................................................................. ........211 5.7.2 bus hold pr ocedur e............................................................................................................. .....212 5.7.3 operation in power save mode ................................................................................................212 5.8 bus priority ................................................................................................................... ........ 213 5.9 bus timing ..................................................................................................................... ....... 214 chapter 6 clock generation function .................... .......................................................... 217 6.1 overview....................................................................................................................... ......... 217 6.2 configuration .................................................................................................................. ...... 218 6.3 registers ...................................................................................................................... ......... 220 6.4 operation...................................................................................................................... ......... 225 6.4.1 operation of each cl ock ........................................................................................................ ...225 6.4.2 clock output functi on .......................................................................................................... .....225 6.5 pll function................................................................................................................... ...... 226 preliminary user?s manual u17717ej2v0ud 11 6.5.1 overvi ew ....................................................................................................................... .......... 226 6.5.2 regist ers ...................................................................................................................... ........... 226 6.5.3 usage .......................................................................................................................... ............ 230 chapter 7 16-bit timer/event counter p (tmp) .. ...............................................................231 7.1 overview....................................................................................................................... ..........231 7.2 functions ...................................................................................................................... .........231 7.3 configuration .................................................................................................................. .......232 7.4 registers ...................................................................................................................... ..........234 7.5 operation...................................................................................................................... ..........248 7.5.1 interval timer mode (tpnmd2 to tpnmd0 bi ts = 000)............................................................. 249 7.5.2 external event count mode (tpn md2 to tpnmd0 bits = 001)................................................. 259 7.5.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) ..................................... 267 7.5.4 one-shot pulse output mode (tpn md2 to tpnmd0 bits = 011) .............................................. 279 7.5.5 pwm output mode (tpnmd2 to tpnmd0 bi ts = 100).............................................................. 286 7.5.6 free-running timer mode (tpnmd2 to tpnmd0 bi ts = 101) .................................................... 295 7.5.7 pulse width measurement mode (tpn md2 to tpnmd0 bits = 110) ........................................ 312 7.5.8 timer output operati ons........................................................................................................ ... 318 7.6 timer tuned operation function .................................. ......................................................319 7.7 selector function .............................................................................................................. ....323 7.8 cautions ....................................................................................................................... ..........325 chapter 8 16-bit timer/event counter q (tmq) ... .............................................................326 8.1 overview....................................................................................................................... ..........326 8.2 functions ...................................................................................................................... .........326 8.3 configuration .................................................................................................................. .......327 8.4 registers ...................................................................................................................... ..........330 8.5 operation...................................................................................................................... ..........348 8.5.1 interval timer mode (tqnmd2 to tqnmd0 bi ts = 000) ............................................................ 349 8.5.2 external event count mode (tqn md2 to tqnmd0 bits = 001) ................................................ 358 8.5.3 external trigger pulse output mode (tqnmd2 to tqnmd0 bits = 010) .................................... 367 8.5.4 one-shot pulse output mode (tqn md2 to tqnmd0 bits = 011) ............................................. 380 8.5.5 pwm output mode (tqnmd2 to tqnmd0 bi ts = 100) ............................................................. 389 8.5.6 free-running timer mode (tqnmd2 to tqnmd0 bi ts = 101) ................................................... 400 8.5.7 pulse width measurement mode (tqn md2 to tqnmd0 bits = 110)........................................ 420 8.5.8 triangular wave pwm mode (t qnmd2 to tqnm d0 = 111) .................................................... 426 8.5.9 timer output operati ons........................................................................................................ ... 427 8.6 timer tuned operation function .................................. ......................................................428 8.7 cautions ....................................................................................................................... ..........432 chapter 9 16-bit interval timer m (tmm).......... ...................................................................433 9.1 overview....................................................................................................................... ..........433 9.2 configuration .................................................................................................................. .......434 9.3 register ....................................................................................................................... ...........435 9.4 operation...................................................................................................................... ..........436 9.4.1 interval ti mer m ode............................................................................................................ ...... 436 9.4.2 cauti ons ....................................................................................................................... ........... 440 preliminary user?s manual u17717ej2v0ud 12 chapter 10 watch timer functions ............................ .......................................................... 441 10.1 functions...................................................................................................................... ......... 441 10.2 configuration .................................................................................................................. ...... 442 10.3 registers ...................................................................................................................... ......... 444 10.4 operation...................................................................................................................... ......... 448 10.4.1 operation as watch ti mer ....................................................................................................... ..448 10.4.2 operation as in terval timer.................................................................................................... ...449 10.4.3 cauti ons....................................................................................................................... ............450 chapter 11 functions of watchdog timer 2 .. ................................................................. 451 11.1 functions...................................................................................................................... ......... 451 11.2 configuration .................................................................................................................. ...... 452 11.3 registers ...................................................................................................................... ......... 453 11.4 operation...................................................................................................................... ......... 456 chapter 12 a/d converter ................................................................................................... ...... 457 12.1 overview....................................................................................................................... ......... 457 12.2 functions...................................................................................................................... ......... 457 12.3 configuration .................................................................................................................. ...... 458 12.4 registers ...................................................................................................................... ......... 461 12.5 operation...................................................................................................................... ......... 469 12.5.1 basic oper ation ................................................................................................................ ........469 12.5.2 trigger mode ................................................................................................................... ........470 12.5.3 operati on m ode ................................................................................................................. ......472 12.5.4 power-fail co mpare mode ........................................................................................................ 476 12.6 cautions ....................................................................................................................... ......... 481 12.7 how to read a/d converter characteristics table... ........................................................ 485 chapter 13 asynchronous serial interface a (uarta) ............................................. 489 13.1 features....................................................................................................................... .......... 490 13.2 configuration .................................................................................................................. ...... 491 13.3 registers ...................................................................................................................... ......... 493 13.4 interrupt request signals.................................................. .................................................. 49 9 13.5 operation...................................................................................................................... ......... 500 13.5.1 data fo rmat .................................................................................................................... ..........500 13.5.2 sbf transmission/rec eption fo rmat ..........................................................................................502 13.5.3 sbf trans missi on............................................................................................................... ......504 13.5.4 sbf rec eptio n .................................................................................................................. ........505 13.5.5 uart trans missi on.............................................................................................................. ....506 13.5.6 continuous transmi ssion proc edure .........................................................................................507 13.5.7 uart rec eptio n ................................................................................................................. ......509 13.5.8 reception errors ............................................................................................................... .......510 13.5.9 parity types and operat ions .................................................................................................... .512 13.5.10 receive data noi se f ilter ...................................................................................................... .....513 13.6 dedicated baud rate generator ......................................................................................... 514 13.7 cautions ....................................................................................................................... ......... 522 chapter 14 3-wire variable-length serial i/o (csib).................................................... 523 preliminary user?s manual u17717ej2v0ud 13 14.1 features....................................................................................................................... ...........523 14.2 configuration .................................................................................................................. .......524 14.3 registers ...................................................................................................................... ..........526 14.4 interrupt request signals......................... ............................................................................5 33 14.5 operation...................................................................................................................... ..........534 14.5.1 single transfer mode (master mode, transmission/rec eption m ode)........................................ 534 14.5.2 single transfer mode (master mode, recept ion m ode)............................................................. 535 14.5.3 continuous mode (master mode, transmission/rec eption m ode)............................................. 536 14.5.4 continuous mode (master m ode, recepti on mode) .................................................................. 537 14.5.5 continuous recepti on mode (e rror) .......................................................................................... 538 14.5.6 continuous mode (slave mode, transmission/rec eption m ode) ............................................... 539 14.5.7 continuous mode (slave m ode, recepti on mode) .................................................................... 540 14.5.8 clock ti ming ................................................................................................................... .......... 541 14.6 output pin status with operation disabled .......... .............................................................543 14.7 operation flow ................................................................................................................. .....544 14.8 baud rate generator ............................................................................................................ 550 14.8.1 baud rate generatio n ........................................................................................................... .... 551 14.9 cautions ....................................................................................................................... ..........552 chapter 15 dma function (dma controller) ..... ...............................................................553 15.1 features....................................................................................................................... ...........553 15.2 configuration .................................................................................................................. .......554 15.3 registers ...................................................................................................................... ..........555 15.4 transfer targets .............................................................. ................................................. .....563 15.5 transfer modes................................................................................................................. .....563 15.6 transfer types................................................................................................................. ......564 15.7 dma channel priorities ........................................................................................................5 65 15.8 time related to dma transfer.............................................................................................565 15.9 dma transfer start factors ............. ....................................................................................566 15.10 dma abort factors.............................................................................................................. ..567 15.11 end of dma transfer............................................................................................................ .567 15.12 operation timing............................................................................................................... ....567 15.13 cautions ....................................................................................................................... ..........572 chapter 16 interrupt/exception processing fu nction ...............................................577 16.1 features....................................................................................................................... ...........577 16.2 non-maskable interrupts .......................... ............................................................................58 1 16.2.1 operat ion...................................................................................................................... ........... 583 16.2.2 restore........................................................................................................................ ............ 584 16.2.3 np fl ag........................................................................................................................ ............. 585 16.3 maskable interrupts ............................................................................................................ ..586 16.3.1 operat ion...................................................................................................................... ........... 586 16.3.2 restore........................................................................................................................ ............ 588 16.3.3 priorities of ma skable inte rrupts .............................................................................................. 589 16.3.4 interrupt control r egister ( xxicn) ............................................................................................. . 593 16.3.5 interrupt mask registers 0 to 4 (imr0 to imr4 )........................................................................ 595 16.3.6 in-service priority register (ispr)............................................................................................ . 597 16.3.7 id flag ........................................................................................................................ .............. 598 preliminary user?s manual u17717ej2v0ud 14 16.3.8 watchdog timer mode regi ster 2 (w dtm2) .............................................................................598 16.4 software exception ............................................................................................................. . 599 16.4.1 operat ion ...................................................................................................................... ...........599 16.4.2 restore ........................................................................................................................ ............600 16.4.3 ep fl ag ........................................................................................................................ .............601 16.5 exception trap................................................................................................................. ..... 602 16.5.1 illegal opcode definit ion ...................................................................................................... .....602 16.5.2 debug tr ap ..................................................................................................................... ..........604 16.6 external interrupt request input pins (nmi a nd intp0 to intp14) ................................. 606 16.6.1 noise elim inatio n .............................................................................................................. .......606 16.6.2 edge detec tion................................................................................................................. ........606 16.7 interrupt acknowledge time of cpu .................................................................................. 615 16.8 periods in which interrupts are not acknowledge d by cpu .......................................... 616 16.9 cautions ....................................................................................................................... ......... 616 chapter 17 key interrupt function ........................... .......................................................... 617 17.1 function....................................................................................................................... .......... 617 17.2 register ....................................................................................................................... .......... 618 17.3 cautions ....................................................................................................................... ......... 618 chapter 18 standby function ................................................................................................ .. 619 18.1 overview....................................................................................................................... ......... 619 18.2 registers ...................................................................................................................... ......... 621 18.3 halt mode...................................................................................................................... ...... 624 18.3.1 setting and operat ion st atus ................................................................................................... .624 18.3.2 releasing ha lt m ode............................................................................................................ .624 18.4 idle1 mode ..................................................................................................................... ...... 626 18.4.1 setting and operat ion st atus ................................................................................................... .626 18.4.2 releasing id le1 m ode ........................................................................................................... .626 18.5 idle2 mode ..................................................................................................................... ...... 628 18.5.1 setting and operat ion st atus ................................................................................................... .628 18.5.2 releasing id le2 m ode ........................................................................................................... .628 18.5.3 securing setup time when releasing id le2 m ode ................................................................... 630 18.6 stop mode...................................................................................................................... ...... 631 18.6.1 setting and operat ion st atus ................................................................................................... .631 18.6.2 releasing st op m ode ............................................................................................................ 631 18.6.3 securing oscillation stabilization ti me when releasi ng stop mode .........................................633 18.7 subclock operation mode ................................................................................................... 634 18.7.1 setting and oper ation st atus ............................................................................................ ........634 18.7.2 releasing subc lock operati on m ode ....................................................................................... .634 18.8 sub-idle mode .................................................................................................................. ... 636 18.8.1 setting and operat ion st atus ................................................................................................... .636 18.8.2 releasing sub- idle m ode .......................................................................................................6 37 chapter 19 reset functions ................................................................................................. .... 639 19.1 overview....................................................................................................................... ......... 639 19.2 registers to check reset source.................................. ..................................................... 640 19.3 operation...................................................................................................................... ......... 641 preliminary user?s manual u17717ej2v0ud 15 19.3.1 reset operation vi a reset pin ............................................................................................... 641 19.3.2 reset operation by watchdog time r 2 ...................................................................................... 643 19.3.3 reset operation by powe r-on clear ci rcuit ................................................................................ 644 19.3.4 reset operation by lo w-voltage det ector .................................................................................. 644 19.3.5 reset operation by clock moni tor ............................................................................................ 644 chapter 20 clock monitor ......................................... .......................................................... ......645 20.1 functions ...................................................................................................................... .........645 20.2 configuration .................................................................................................................. .......645 20.3 register ....................................................................................................................... ...........646 20.4 operation...................................................................................................................... ..........647 chapter 21 power-on clear circ uit .....................................................................................650 21.1 function ....................................................................................................................... ..........650 21.2 configuration .................................................................................................................. .......650 21.3 operation...................................................................................................................... ..........651 chapter 22 low-voltage detector.............................. ..........................................................652 22.1 functions ...................................................................................................................... .........652 22.2 configuration .................................................................................................................. .......652 22.3 registers ...................................................................................................................... ..........653 22.4 operation...................................................................................................................... ..........655 22.4.1 to use for inter nal rese t signal ............................................................................................... . 655 22.4.2 to use for interr upt ........................................................................................................... ....... 657 22.5 ram retention voltage detection operation........... ..........................................................658 22.6 emulation function............................................................................................................. ..659 chapter 23 regulator ........................................................................................................ ..........660 23.1 overview....................................................................................................................... ..........660 23.2 operation...................................................................................................................... ..........661 chapter 24 flash memory.................................................................................................... .......662 24.1 features....................................................................................................................... ...........662 24.1.1 erasure unit ................................................................................................................... .......... 663 24.2 rewriting by dedicated flash programmer ............. ..........................................................664 24.2.1 programming env ironment ...................................................................................................... 66 4 24.2.2 communicati on m ode............................................................................................................. . 665 24.2.3 flash memory cont rol ........................................................................................................... ... 670 24.2.4 selection of comm unication mode ........................................................................................... 671 24.2.5 communication commands ..................................................................................................... 672 24.2.6 pin connec tion ................................................................................................................. ........ 673 24.2.7 recommended circuit exam ple for wr iting ............................................................................... 677 24.3 rewriting by self programming............... ............................................................................678 24.3.1 overvi ew ....................................................................................................................... .......... 678 24.3.2 featur es ....................................................................................................................... ........... 679 24.3.3 standard self progr amming fl ow .............................................................................................. 680 24.3.4 flash f uncti ons ................................................................................................................ ........ 681 24.3.5 pin proc essi ng ................................................................................................................. ........ 681 preliminary user?s manual u17717ej2v0ud 16 24.3.6 internal res ources used ........................................................................................................ ...682 chapter 25 option byte function ............................ .............................................................. 6 83 chapter 26 on-chip debug function ........................... .......................................................... 684 26.1 features....................................................................................................................... .......... 684 26.2 connection circuit example................................................................................................ 685 26.3 interface signals .............................................................................................................. ..... 686 26.4 register ....................................................................................................................... .......... 688 26.5 operation...................................................................................................................... ......... 689 26.6 rom security function........................................................................................................ 69 0 26.6.1 security id .................................................................................................................... ...........690 26.6.2 setti ng ........................................................................................................................ .............691 26.7 cautions ....................................................................................................................... ......... 692 chapter 27 electrical specifications (target) .............................................................. 693 27.1 electrical specifications ...................................................................................................... 693 27.2 capacitance.................................................................................................................... ....... 695 27.3 operating conditions........................................................................................................... 695 27.4 oscillator characteristics .................................................................................................... 6 96 27.4.1 main clock oscillator characteri stics .........................................................................................6 96 27.4.2 subclock oscillator c haracterist ics ...........................................................................................6 97 27.4.3 pll characte ristics ............................................................................................................ ......698 27.4.4 internal oscillator characteri stics............................................................................................ ..698 27.5 voltage regulator characteristics................................. ..................................................... 698 27.6 dc characteristics ............................................................................................................. .. 699 27.6.1 i/o level ...................................................................................................................... .............699 27.6.2 pin leakage curr ent ............................................................................................................ ......700 27.6.3 supply cu rrent................................................................................................................. .........701 27.7 data retention characteristics ................................... ........................................................ 703 27.8 ac characteristics ............................................................................................................. .. 704 27.8.1 clkout out put ti ming........................................................................................................... 705 27.8.2 bus ti ming..................................................................................................................... ..........706 27.9 basic operation ................................................................................................................ .... 711 27.10 flash memory programming characteristics............... ..................................................... 718 chapter 28 package drawing ................................................................................................. . 719 appendix a register index .................................................................................................. ....... 720 appendix b instruction set list ........................................................................................... .. 731 b.1 conventions .................................................................................................................... ...... 731 b.2 instruction set (in alphabetical order) ...................... ........................................................ 734 preliminary user?s manual u17717ej2v0ud 17 chapter 1 introduction the v850es/hj2 is one of the products in the nec el ectronics v850 series of single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 general the v850es/hj2 is a 32-bit single-chip microcontroller that includes the v850es cpu core and peripheral functions such as rom/ram, a timer/counter, serial interfaces, and an a/d converter. in addition to high real-time response characteristics and 1-clock-pitch basic instructio ns, the v850es/hj2 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. table 1-1 lists the produc ts of the v850es/hj2. chapter 1 introduction preliminary user?s manual u17717ej2v0ud 18 table 1-1. v850es/hj2 product list part number pd70f3709 pd70f3710 pd70f3711 pd70f3712 flash memory 128 kb 256 kb 376 kb 512 kb internal memory ram 12 kb 20 kb logical space 64 mb memory space external memory area 15 mb external bus interface address bus: 16 bits data bus: 8/16 bits multiplexed bus mode general-purpose register 32 bits 32 registers main clock (oscillation frequency) ceramic/crystal/external clock ? in pll mode: f x = 4 to 5 mhz ? in clock through mode: f x = 4 to 5 mhz subclock (oscillation frequency) crystal/external clock: f xt = 32.768 khz rc oscillation: 20 khz internal oscillator f r = 200 khz (typ.) minimum instruction executi on time 50 ns (main clock (f xx ) = 20 mhz operation) dsp function 32 32 = 64: 200 to 250 ns (at 20 mhz) 32 32 + 32 = 32: 300 ns (at 20 mhz) 16 16 = 32: 50 to 100 ns (at 20 mhz) 16 16 + 32 = 32: 150 ns (at 20 mhz) i/o port i/o: 128 timer 16-bit timer/event counter p: 4 channels 16-bit timer/event counter q: 3 channels 16-bit interval timer m: 1 channel watchdog timer 2: 1 channel watch timer: 1 channel a/d converter 10-bit resolution 24 channels serial interface csib: 3 channels uarta (for lin): 3 channels csib: 3 channels uarta (for lin): 4 channels dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram, external memory) interrupt source external: 16 (16) note , internal: 50 external: 16 (16) note , internal: 52 power save function halt/idle1/idle2/stop/subclock/sub-idle mode reset reset pin input, watchdog timer 2 (wdt2), cl ock monitor (clm), poc circuit, low-voltage detector (lvi) on-chip debug function provided (run/break) operating power supply voltage 3.5 to 5.5 v (a/d converter: 4.0 to 5.5 v) operating ambient temperature ? 40 to +85 c package 144-pin plastic lqfp (fine pitch) (20 20 mm) note the figure in parentheses indicates the number of external interrupts that can release stop mode. chapter 1 introduction preliminary user?s manual u17717ej2v0ud 19 1.2 features minimum instruction execution time: 50 ns (operating with main clock (f xx ) of 20 mhz) general-purpose registers: 32 bits 32 registers cpu features: signed multiplication (16 16 32): 1 to 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format memory space: 64 mb of linear address space (for programs and data) external expansion: up to 256 kb (including 64 kb used as internal rom/ram) ? internal memory: ram: 12 kb/20 kb (see table 1-1 ) flash memory: 128 kb/256 kb/376 kb/512 kb (see table 1-1 ) ? external bus interface: multiplexed bus output 8-/16-bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function interrupts and exceptions: non-maskable interrupts: 2 sources maskable interrupts: 64/66 sources (see table 1-1 ) software exceptions: 32 sources exception trap: 2 sources i/o lines: i/o ports: 128 timer function: 16-bit interv al timer m (tmm): 1 channel 16-bit timer/event counter p (tmp): 4 channels 16-bit timer/event counter q (tmq): 3 channels watch timer: 1 channel watchdog timer 2: 1 channel serial interface: asynchronous serial interface a (uarta) 3-wire variable-length serial interface b (csib) uarta (supporting lin): 4 channels ( pd70f3711, 70f3712) 3 channels ( pd70f3709, 70f3710) csib: 3 channels a/d converter: 10-bit resolution: 24 channels dma controller: 4 channels on-chip debug function: jtag interface clock generator: during main clock or subclock operation 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable internal oscillation clock: 200 khz (typ.) power-save functions: halt/idle1/idle2/stop/subclock/sub-idle mode package: 144-pin plastic lqfp (fine pitch) (20 20) 1.3 application fields consumer devices chapter 1 introduction preliminary user?s manual u17717ej2v0ud 20 1.4 ordering information part number package on-chip flash memory pd70f3709gj-uen-a pd70f3710gj-uen-a pd70f3711gj-uen-a pd70f3712gj-uen-a 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 128 kb 256 kb 376 kb 512 kb remark products with -a at the end of t he part number are lead-free products. chapter 1 introduction preliminary user?s manual u17717ej2v0ud 21 1.5 pin configuration (top view) 144-pin plastic lqfp (fine pitch) (20 20) pd70f3709gj-uen-a pd70f3710gj-uen-a pd70f3711gj-uen-a pd70f3712gj-uen-a av ref0 av ss p10/intp9 p11/intp10 ev dd p00/tip31/top31 p01/tip30/top30 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst p06/intp3 p40/sib0 p41/sob0 p42/sckb0 p30/txda0 p31/rxda0/intp7 p32/ascka0/tip00/top00/top01 p33/tip01/top01 p34/tip10/top10 p35/tip11/top11 p36 p37 ev ss ev dd p38/txda2 p39/rxda2/intp8 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0/cs0 pcd3 pcd2 pcd1 pcd0 p915/intp6 p914/intp5 p913/intp4/pcl p912/sckb2 p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms p60/intp11 p61/intp12 p62/intp13 p63 p64 p65 p66 p67 p68 p69 p610/tiq20/toq20 p611/tiq21/toq21 p612/tiq22/toq22 p613/tiq23/toq23 p614 p615 p80/rxda3 note 3 /intp14 p81/txda3 note 3 p90/kr6/txda1 p91/kr7/rxda1 p92/tiq11/toq11 p93/tiq12/toq12 p94/tiq13/toq13 p95/tiq10/toq10 p96/tip21/top21 p97/sib1/tip20/top20 p98/sob1 p99/sckb1 p910/sib2 p911/sob2 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p712/ani12 p713/ani13 p714/ani14 p715/ani15 p120/ani16 p121/ani17 p122/ani18 p123/ani19 p124/ani20 p125/ani21 p126/ani22 p127/ani23 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 notes 1. connect this pin to v ss in the normal mode. 2. connect the regc pin to v ss via a 4.7 f (preliminary value) capacitor. 3. pd70f3711, 70f3712 only chapter 1 introduction preliminary user?s manual u17717ej2v0ud 22 pin identification ad0 to ad15: adtrg: ani0 to ani23: ascka0: astb: av ref0 : av ss : bv dd : bv ss : clkout: cs0 to cs3: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: intp0 to intp14: kr0 to kr7: nmi: p00 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p60 to p615: p70 to p715: p80, p81: p90 to p915: p120 to p127: pcd0 to pcd3: address/data bus a/d trigger input analog input asynchronous serial clock address strobe analog reference voltage analog v ss power supply for bus interface ground for bus interface clock output chip select debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request external interrupt request key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port 12 port cd pcl: pcm0 to pcm5: pcs0 to pcs7: pct0 to pct7: pdl0 to pdl15: rd: regc: reset: rxda0 to rxda3: sckb0 to sckb2: sib0 to sib2: sob0 to sob2: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tiq00 to tiq03, tiq10 to tiq13, tiq20 to tiq23: top00, top01, top10, top11, top20, top21, top30, top31, toq00 to toq03, toq10 to toq13, toq20 to toq23: txda0 to txda3: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: programmable clock output port cm port cs port ct port dl read strobe regulator control reset receive data serial clock serial input serial output timer input timer output transmit data power supply ground wait write strobe low level data write strobe high level data crystal for main clock crystal for subclock chapter 1 introduction preliminary user?s manual u17717ej2v0ud 23 1.6 function block configuration 1.6.1 internal block diagram nmi toq00 to toq03 toq10 to toq13 toq20 to toq23 tiq00 to tiq03 tiq10 to tiq13 tiq20 to tiq23 intp0 to intp14 intc 16-bit timer/ counter q: 3 ch top00 to top30, top01 to top31 tip00 to tip30, tip01 to tip31 16-bit timer/ counter p: 4 ch sob0 to sob2 sib0 to sib2 csib: 3 ch kr0 to kr7 dmac key return function note 1 note 2 ram flash memory pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 ad0 to ad15 flmd0 flmd1 ports cg regulator pll lvi internal oscillator clm cs0 to cs3 pcs0 to pcs7 pcm0 to pcm5 pct0 to pct7 pdh0 to pdh7 pdl0 to pdl15 pcd0 to pcd3 p90 to p915 p80, p81 p70 to p715 p60 to p615 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 ani0 to ani23 av ss av ref0 adtrg clkout xt1 xt2 x1 x2 reset v dd v ss regc bv dd bv ss ev dd ev ss instruction queue bcu 16-bit interval timer m: 1 ch on-chip debug function drst dms ddi dck ddo a/d converter poc sckb0 to sckb2 rxda0 to rxda3 note 3 txda0 to txda3 note 3 uarta: 4 ch note 3 asck0 watchdog timer 2 watch timer notes 1. pd70f3709: 128 kb pd70f3710: 256 kb pd70f3711: 376 kb pd70f3712: 512 kb 2. pd70f3709, 70f3710: 12 kb pd70f3711, 70f3712: 20 kb 3. pd70f3709, 70f3710: 3 channels chapter 1 introduction preliminary user?s manual u17717ej2v0ud 24 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single -clock execution of addres s calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtai ned by the cpu. when an instruction is fetched from external memory space a nd the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the pref etched instruction code is stored in an instruction queue. (3) rom this is a 512 kb/376 kb/256 kb/128 kb flash memory mapped to addresses 0000000h to 007ffffh/0000000h to 005dfffh/0000000h to 003ffffh /0000000h to 001ffffh. it can be accessed from the cpu in one clock during instruction fetch. (4) ram this is a 20 kb/12 kb ram mapped to addresses 3f fa000h to 3ffefffh/3ffc000h to 3ffefffh. it can be accessed from the cpu in one clock during data access. (5) interrupt controller (intc) this controller handles hardware interrupt requests (n mi, intp0 to intp14) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiple servicing control can be performed. (6) clock generator (cg) a main clock oscillator that generates the main clock oscillation frequency (f x ) and a subclock oscillator that generates the subclock oscillation frequency (f xt ) are available. as the main clock frequency (f xx ), f x is used as is in the clock-through mode and is multiplied by four in the pll mode. the cpu clock frequency (f cpu ) can be selected from seven types: f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (7) internal oscillator an internal oscillator is provided on chip. the oscillation frequency is 200 khz (typ.). an internal oscillator supplies the clock for watchdog timer 2 and timer m. (8) timer/counter four-channel 16-bit timer/event counter p (tmp), thr ee-channel 16-bit timer/event counter q (tmq), and one- channel 16-bit interval timer m (tmm) are provided on chip. (9) watch timer this timer counts the reference time period (0.5 s) for counting the clock (the 32.768 khz from the subclock or the 32.768 khz f brg from prescaler 3). the watch timer can also be used as an interval timer for the main clock. chapter 1 introduction preliminary user?s manual u17717ej2v0ud 25 (10) watchdog timer 2 a watchdog timer is provided on chip to detect inadv ertent program loops, system abnormalities, etc. either the internal oscillation clock or the main clock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt request signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. (11) serial interface the v850es/hj2 includes three kinds of serial interfaces: asynchronous serial interface a (uarta) and 3- wire variable-length serial interface b (csib). in the case of uarta, data is transferred via the txdan and rxdan pins. (n = 0 to 3: pd70f3711, 70f3712, n = 0 to 2: pd70f3709, 70f3710) in the case of csib, data is transferred via the sob0 to sob3 pins, sib0 to sib3 pins, and sckb0 to sckb3 pins. (12) a/d converter this 10-bit a/d converter includes 24 analog input pins. conversion is performed using the successive approximation method. (13) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram and on-chip peripheral i/o devices in resp onse to interrupt requests sent by on-chip peripheral i/o. (14) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to key input pins (8 channels). (15) on-chip debug function an on-chip debug function that uses the jtag (joint test action group) communication specifications is provided. switching between the normal port function and on-chip debugging function is done with the control pin input level and the on-chip debug mode register (ocdm). (16) ports the general-purpose port functions and control pin functions are provided. for details, see chapter 4 port functions . preliminary user?s manual u17717ej2v0ud 26 chapter 2 pin functions this section explains the names and func tions of the pins of the v850es/hj2. 2.1 pin function list three i/o buffer power supplies, av ref0 , bv dd , and ev dd , are available. the relationship between the power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pin av ref0 port 7, port 12 bv dd port cd, port cm, port cs, port ct, port dl ev dd port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9, reset (1) port pins table 2-2. list of pins (port pins) (1/3) pin name i/o function alternate function p00 tip31/top31 p01 tip30/top30 p02 nmi p03 intp0/adtrg p04 intp1 p05 intp2/drst p06 i/o port 0 7-bit i/o port input/output can be specified in 1-bit units. intp3 p10 intp9 p11 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. intp10 p30 txda0 p31 rxda0/intp7 p32 ascka0/tip00/top00/top01 p33 tip01/top01 p34 tip10/top10 p35 tip11/top11 p36 ? p37 ? p38 txda2 p39 i/o port 3 10-bit i/o port input/output can be specified in 1-bit units. rxda2/intp8 p40 sib0 p41 sob0 p42 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. sckb0 chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 27 table 2-2. list of pins (port pins) (2/3) pin name i/o function alternate function p50 kr0/tiq01/toq01 p51 kr1/tiq02/toq02 p52 kr2/tiq03/toq03/ddi p53 kr3/tiq00/toq00/ddo p54 kr4/dck p55 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. kr5/dms p60 intp11 p61 intp12 p62 intp13 p63 ? p64 ? p65 ? p66 ? p67 ? p68 ? p69 ? p610 tiq20/toq20 p611 tiq21/toq21 p612 tiq22/toq22 p613 tiq23/toq23 p614 ? p615 i/o port 6 16-bit i/o port input/output can be specified in 1-bit units. ? p70 to p715 i/o port 7 16-bit i/o port input/output can be specified in 1-bit units. ani0 to ani15 p80 rxda3 note /intp14 p81 i/o port 8 2-bit i/o port input/output can be specified in 1-bit units. txda3 note note pd70f3711, 70f3712 only chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 28 table 2-2. list of pins (port pins) (3/3) pin name i/o function alternate function p90 kr6/txda1 p91 kr7/rxda1 p92 tiq11/toq11 p93 tiq12/toq12 p94 tiq13/toq13 p95 tiq10/toq10 p96 tip21/top21 p97 sib1/tip20/top20 p98 sob1 p99 sckb1 p910 sib2 p911 sob2 p912 sckb2 p913 intp4/pcl p914 intp5 p915 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. intp6 p120 to p127 i/o port 12 8-bit i/o port input/output can be specified in 1-bit units. ani16 to ani23 pcd0 to pcd3 i/o port cd 4-bit i/o port input/output can be specified in 1-bit units. ? pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq pcm4 ? pcm5 i/o port cm 6-bit i/o port input/output can be specified in 1-bit units. ? pcs0 to pcs3 cs0 to cs3 pcs4 to pcs7 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. ? pct0 wr0 pct1 wr1 pct2 ? pct3 ? pct4 rd pct5 ? pct6 astb pct7 i/o port ct 8-bit i/o port input/output can be specified in 1-bit units. ? pdl0 to pdl4 ad0 to ad4 pdl5 ad5/flmd1 pdl6 to pdl15 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad6 to ad15 chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 29 (2) non-port pins table 2-3. list of pins (non-port pins) (1/4) pin name i/o function alternate function nmi note 1 input external interrupt input (non-maskable, with analog noise eliminated) p02 intp0 p03/adtrg intp1 p04 intp2 p05/drst intp3 p06 intp4 p913/pcl intp5 p914 intp6 p915 intp7 p31/rxda0 intp8 p39/rxda2 intp9 p10 intp10 p11 intp11 p60 intp12 p61 intp13 p62 intp14 input external interrupt request input (maskable, with analog noise eliminated) p80/rxda3 note 2 tip00 external event/clock input (tmp00) p32/ascka0/top00/top01 tip01 external event input (tmp01) p33/top01 tip10 external event/clock input (tmp10) p34/top10 tip11 external event input (tmp11) p35/top11 tip20 external event/clock input (tmp20) p97/sib1/top20 tip21 external event input (tmp21) p96/top21 tip30 external event/clock input (tmp30) p01/top30 tip31 input external event input (tmp31) p00/top31 top00 timer output (tmp00) p32/ascka0/tip00/top01 p32/ascka0/tip00/top00 top01 timer output (tmp01) p33/tip01 top10 timer output (tmp10) p34/tip10 top11 timer output (tmp11) p35/tip11 top20 timer output (tmp20) p97/sib1/tip20 top21 timer output (tmp21) p96/tip21 top30 timer output (tmp30) p01/tip30 top31 output timer output (tmp31) p00/tip31 notes 1. the nmi pin alternately functions as t he p02 pin. it functions as the p02 pin after reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using intf0 and intr0 registers. 2. pd70f3711, 70f3712 only chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 30 table 2-3. list of pins (non-port pins) (2/4) pin name i/o function alternate function tiq00 external event/clock input (tmq00) p53/kr3/toq00/ddo tiq01 external event input (tmq01) p50/kr0/toq01 tiq02 external event input (tmq02) p51/kr1/toq02 tiq03 external event input (tmq03) p52/kr2/toq03/ddi tiq10 external event/clock input (tmq10) p95/toq10 tiq11 external event input (tmq11) p92/toq11 tiq12 external event input (tmq12) p93/toq12 tiq13 external event input (tmq13) p94/toq13 tiq20 external event/clock input (tmq20) p610/toq20 tiq21 external event input (tmq21) p611/toq21 tiq22 external event input (tmq22) p612/toq22 tiq23 input external event input (tmq23) p613/toq23 toq00 timer output (tmq00) p53/kr3/tiq00/ddo toq01 timer output (tmq01) p50/kr0/tiq01 toq02 timer output (tmq02) p51/kr1/tiq02 toq03 timer output (tmq03) p52/kr2/tiq03/ddi toq10 timer output (tmq10) p95/tiq10 toq11 timer output (tmq11) p92/tiq11 toq12 timer output (tmq12) p93/tiq12 toq13 timer output (tmq13) p94/tiq13 toq20 timer output (tmq20) p610/tiq20 toq21 timer output (tmq21) p611/tiq21 toq22 timer output (tmq22) p612/tiq22 toq23 output timer output (tmq23) p613/tiq23 sib0 serial receive data input (csib0) p40 sib1 serial receive data input (csib1) p97/tip20/top20 sib2 input serial receive data input (csib2) p910 sob0 serial transmit data output (csib0) p41 sob1 serial transmit data output (csib1) p98 sob2 output serial transmit data output (csib2) p911 sckb0 serial clock i/o (csib0) p42 sckb1 serial clock i/o (csib1) p99 sckb2 i/o serial clock i/o (csib2) p912 rxda0 serial receive data input (uarta0) p31/intp7 rxda1 serial receive data input (uarta1) p91/kr7 rxda2 serial receive data input (uarta2) p39/intp8 rxda3 note input serial receive data input (uarta3) p80/intp14 note pf70f3711, 70f3712 only chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 31 table 2-3. list of pins (non-port pins) (3/4) pin name i/o function alternate function txda0 serial transmit data output (uarta0) p30 txda1 serial transmit data output (uarta1) p90/kr6 txda2 serial transmit data output (uarta2) p38 txda3 note output serial transmit data output (uarta3) p81 ascka0 input baud rate clock input to uarta0 p32/tip00/top00/top01 ani0 to ani15 p70 to p715 ani16 to ani23 input analog voltage input to a/d converter p120 to p127 av ref0 input reference voltage input to a/d converter, positive power supply for alternate-function port 7 ? av ss ? ground potential for a/d and d/a converters (same potential as v ss ) ? adtrg input a/d converter external trigger input p03/intp0 kr0 p50/tiq01/toq01 kr1 p51/tiq02/toq02 kr2 p52/tiq03/toq03/ddi kr3 p53/tiq00/toq00/ddo kr4 p54/dck kr5 p55/dms kr6 p90/txda1 kr7 input key interrupt input p91/rxda1 dms input debug mode select p55/kr5 ddi input debug data input p52/kr2/tiq03/toq03 ddo output debug data output p53/kr3/tiq00/toq00 dck input debug clock input p54/kr4 drst input debug reset input p05/intp2 cs0 to cs3 output chip select signal output pcs0 to pcs3 ad0 to ad4 pdl0 to pdl4 ad5 pdl5/flmd1 ad6 to ad15 i/o address/data bus for external memory pdl6 to pdl15 astb output address strobe signal output for external memory pct6 hldrq input bus hold request input pcm3 hldak output bus hold acknowledge output pcm2 rd output read strobe signal output for external memory pct4 wait input external wait input pcm0 wr0 write strobe for external memory (lower 8 bits) pct0 wr1 output write strove for external memory (higher 8 bits) pct1 flmd0 ? flmd1 input flash programming mode setting pins pdl5/ad5 clkout output internal system clock output pcm1 note pf70f3711, 70f3712 only chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 32 table 2-3. list of pins (non-port pins) (4/4) pin name i/o function alternate function pcl output clock output (timing output of x1 input clock and subclock) p913/intp4 regc ? regulator output stabilizing capacitor connection ? reset input system reset input ? x1 input ? x2 ? main clock resonator connection ? xt1 input ? xt2 ? subclock resonator connection ? v dd ? positive power supply pin for internal circuitry ? v ss ? ground potential for internal circuitry ? bv dd ? positive power supply pin for bus interface and alternate-function ports ? bv ss ? ground potential for bus interface and alternate-function ports ? ev dd ? positive power supply pin for exter nal circuitry (same potential as v dd ) ? ev ss ? ground potential for external circuitry (same potential as v ss ) ? chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 33 2.2 pin status the v850es/hj2 has an external bus interface function t hat enables connection of external memories, such as rom and ram, and i/o. table 2-4 shows the operating stat us of each external bus interf ace pin in each operation mode. table 2-4. pin operating stat us in each operation mode bus control pin reset halt mode and dma transfer idle1, idle2, and stop modes idle state note 2 bus hold ad0 to ad15 hi-z cs0 to cs3 h held hi-z wait ? ? ? clkout l operating operating wr0, wr1 rd astb hi-z hldak h h l hldrq hi-z note 1 operating ? ? operating notes 1. the bus control pins function alternately as port pi ns and are initialized to the input mode (port mode). 2. pin status in the idle state that is inserted after the t3 state. remark hi-z: high impedance held: the state during the immediatel y preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged) chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 34 2.3 description of pin functions (1) p00 to p06 (port 0) ? 3-state i/o p00 to p06 function as a 7-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as nmi input, external interrupt request signal input, timer/counter i/o, external trigger of t he a/d converter, an d debug reset input. this port can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by the intr0 and intf0 registers. an on-chip pull-up resistor can be connected to p00 to p06 by using pull-up resistor option register 0 (pu0). (a) port mode p00 to p06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (pm0). (b) control mode (i) nmi (non-maskable in terrupt request) ? input this pin inputs a non-maskable interrupt request signal. (ii) intp0 to intp3 (external interrupt request) ? input these pins input external interrupt request signals. (iii) tip30, tip31 (timer input) ? input these pins input an external count clock to timer p3 (tmp3). (iv) top30, top31 (timer output) ? output these pins output a pulse signal from timer p3 (tmp3). (v) adtrg (a/d trigger input) ? input this pin inputs an external trigger to the a/d conver ter. it is controlled by using a/d converter mode register 0 (ada0m0). (vi) drst (debug reset) ? input this pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip debug circuit. to deassert this signal, reset or in validate the on-chip debug circuit. deassert this signal when the debug function is not used. for details, see chapter 26 on-chip debug function . chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 35 (2) p10, p11 (port 1) ? 3-state i/o p10 and p11 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input in the control mode. this port can be set in the port mode or cont rol mode in 1-bit units. the valid edge of each pin is specified by intr1 and intf1 registers. an on-chip pull-up resistor can be connected to p10 and p11 by using pull-up resistor option register 1 (pu1). (a) port mode p10 and p11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (pm1). (b) control mode (i) intp9, intp10 (external interrupt request) ? input these pins input an external interrupt request signal. (3) p30 to p39 (port 3) ? 3-state i/o p30 to p39 function as a 10-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input, serial interface i/o, and timer/counter i/o. this port can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by the intr3 and intf3 registers. an on-chip pull-up resistor can be connected to p30 to p39 by using pull-up resistor option register 3 (pu3). (a) port mode p30 to p39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (pm3). (b) control mode (i) rxda0, rxda2 (receive data) ? input these pins input the serial receive data of uarta0 and uarta2. (ii) txda0, txda2 (transmit data) ? output these pins output the serial trans mit data of uarta0 and uarta2. (iii) ascka0 (asynchronous serial clock) ? input this is an input pin for uarta0. (iv) intp7, intp8 (external interrupt request) ? input these pins input an external interrupt request signal. (v) tip00, tip01, tip10, tip11 (timer input) ? input these are input pins for timers p0 and p1 (tmp0 and tmp1). (vi) top00, top01, top10, top11 (timer output) ? output these are output pins for timers p0 and p1 (tmp0 and tmp1). chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 36 (4) p40 to p42 (port 4) ? 3-state i/o p40 to p42 function as a 3-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o. this port can be set in the port mode or control mode in 1-bit units. an on-chip pull-up resistor can be connected to p40 to p42 by using pull-up resistor option register 4 (pu4). (a) port mode p40 to p42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (pm4). (b) control mode (i) sib0 (serial input) ? input this pin inputs the serial receive data of csib0. (ii) sob0 (serial output) ? output this pin outputs the serial transmit data of csib0. (iii) sckb0 (serial clock) ? 3-state i/o this pin inputs/outputs the serial clock of csib0. (5) p50 to p55 (port 5) ? 3-state i/o p50 to p55 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins oper ate as timer/counter i/o, debug function i/o, and key interrupt input. this port can be set in the port mode or control mode in 1-bit units. an on-chip pull-up resistor can be connected to p50 to p55 by using pull-up resistor option register 5 (pu5). (a) port mode p50 to p55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (pm5). (b) control mode (i) kr0 to kr5 (key return) ? input these pins input a key interrupt. their operation is specified by using the key return mode register (krm) in the input port mode. (ii) tiq00, tiq01, tiq02, tiq03 (timer input) ? input these are input pins for timer q0 (tmq0). (iii) toq00, toq01, toq02, toq03 (timer output) ? output these are output pins for timer q0 (tmq0). (iv) ddi (debug data input) ? input this pin inputs debug data to the on-chip debug circuit. for details, see chapter 26 on-chip debug function . (v) ddo (debug data output) ? output this pin outputs debug data from the on-chip debug circuit. for details, see chapter 26 on-chip debug function . chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 37 (iv) dck (debug clock input) ? input this pin inputs a debug clock to the on-chip debug circuit. for details, see chapter 26 on-chip debug function . (vii) dms (debug mode select) ? input this pin selects the debug mode of the on-chip debug circuit. for details, see chapter 26 on-chip debug function . (6) p60 to p615 (port 6) ? 3-state i/o p60 to p615 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operat e as external interrupt request signal input and timer/counter i/o. p60 to p62 can be set in the port mode or control mode in 1-bit units. the valid edge of p60 to p615 is specified by intr6l and intf6l registers. an on-chip pull-up resistor can be connected to p60 to p615 by using pull-up resistor option register 6 (pu6). (a) port mode p60 to p615 can be set in the input or output mode in 1-bit units, by using port mode register 6 (pm6). (b) control mode (i) intp11 to intp13 (externa l interrupt request) ? input these pins input an external interrupt request signal. (ii) tiq20, tiq21, tiq22, tiq23 (timer input) ? input these are input pins for timer q2 (tmq2). (iii) toq20, toq21, toq22, toq23 (timer output) ? output these are output pins for timer q2 (tmq2). (7) p70 to p715 (port 7) ? 3-state i/o p70 to p715 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as anal og input to the a/d conver ter in the control mode. when using the analog input pins, however, set this port in the input mode. at this time, do not read the port. (a) port mode p70 to p715 can be set in the input or output mode in 1-bit units, by using port mode registers 7l and 7h (pm7l and pm7h). (b) control mode p70 to p715 function alternately as the ani0 to ani15 pins. (i) ani0 to ani15 (analog input 0 to 15) ? input these pins input an analog signal to the a/d converter. chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 38 (8) p80 and p81 (port 8) ? 3-state i/o p80 and p81 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operat e as external interrupt request signal input, and serial interface i/o. p80 and p81 can be set in the port mode or control mode in 1-bit units. the valid edge of each pin is specified by intr8 and intf8 registers. an on-chip pull-up resistor can be connected to p80 and p81 by using pull-up resistor option register 8 (pu8). (a) port mode p80 and p81 can be set in the input or output mode in 1-bit units, by using port mode register 8 (pm8). (b) control mode (i) intp14 (external interrupt request) ? input this pin inputs an external interrupt request signal. (ii) rxda3 (receive data) note ? input this pin inputs the serial receive data of uarta3. (iii) txda3 (transmit data) note ? output this pin outputs the serial transmit data of uarta3. note pd70f3711 and 70f3712 only (9) p90 to p915 (port 9) ? 3-state i/o p90 to p915 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o, ti mer/counter i/o, clock output, external interrupt request signal input, and key interrupt input. this port can be set in the port mode or control mode in 1-bit units. the valid edge of p913 to p915 is specified by intr9h and intf9h registers. an on-chip pull-up resistor can be connected to p90 to p915 by using pull-up resistor option register 9 (pu9). (a) port mode p90 to p915 can be set in the input or output mode in 1-bit units, by using port mode register 9 (pm9). (b) control mode (i) sib1, sib2 (serial input) ? input these pins input the serial receive data of csib1 and csib2. (ii) sob1, sob2 (serial output) ? output these pins output the serial tr ansmit data of csib1 and csib2. (iii) sckb1, sckb2 (serial clock) ? 3-state i/o these pins input/output the seri al clock of csib1 and csib2. (iv) rxda1 (receive data) ? input this pin inputs the serial receive data of uarta1. chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 39 (v) txda1 (transmit data) ? output this pin outputs the serial transmit data of uarta1. (vi) tip20, tip21 (timer input) ? input these are input pins for timer p2 (tmp2). (vii) top20, top21 (timer output) ? output these are output pins for timer p2 (tmp2). (viii) tiq10, tiq11, tiq12, tiq13 (timer input) ? input these are input pins for timer q1 (tmq1). (ix) toq10, toq11, toq12, toq13 (timer output) ? output these are output pins for timer q1 (tmq1). (x) pcl (clock output) ? output this pin outputs a clock. (xi) intp4 to intp6 (externa l interrupt request) ? input these pins input an external interrupt request signal. (xii) kr6, kr7 (key return) ? input these pins input a key interrupt. their operation is specified by the key return mode register (krm) in the input port mode. (10) p120 to p127 (port 12) ? 3-state i/o p120 to p127 function as an 8-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as the analog input pins of the a/d converter in the control mode. when using this port as analog input pins, ho wever, set the port in the input mode. at this time, do not read the port. (a) port mode p120 to p127 can be set in the input or output mode in 1-bit units, by using port mode register 12 (pm12). (b) control mode p120 to p127 function alternately as the ani16 to ani23 pins. (i) ani16 to ani23 (analog input 16 to 23) ? input these pins input an analog signal to the a/d converter. (11) pcd0 to pcd3 (port cd) ? 3-state i/o pcd0 to pcd3 function as a 4-bit i/o port that can be set to input or output in 1-bit units. (a) port mode pcd0 to pcd3 can be set in the input or output mo de in 1-bit units, by using port mode register cd (pmcd). chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 40 (12) pcm0 to pcm5 (port cm) ? 3-state i/o pcm0 to pcm5 function as a 6-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as bus hold control signal i/o, bus clock output, and a control signal that in serts a wait cycle in the bus cycle (wait), in the control mode. (a) port mode pcm0 to pcm5 can be set in the input or output mo de in 1-bit units, by using port mode register cm (pmcm). (b) control mode (i) hldak (hold acknowledge) ? output this pin outputs an acknowledge signal that indica tes that the v850es/hj2 has placed the address bus, data bus, and control bus in a high-impedance state in response to a bus hold request. while this signal is active, the address bus, data bus , and control bus go into a high-impedance state. (ii) hldrq (hold request) ? input an external device uses this input pin to req uest the v850es/hj2 to release the address bus, data bus, and control bus. a signal can be input to this pin asynchronously to clkout. when this pin is asserted, the v850es/hj2 places the address bus, data bus, and control bus in a high-impedance state after completion of a bus cycle under execution, if any, or immediately if no such bus cycle is under execution. the v850e s/hj2 then asserts the hldak signal and releases the buses. (iii) clkout (clock output) ? output this pin outputs an internally generated bus clock. (iv) wait (wait) ? input this is a control signal input pin that inserts a data wait state in the bus cycle. a signal can be input to this pin asynchronously to the clkout signal. the signal input to this pin is sampled at the falling edge of the clkout signal in the t2 and tw states of the bus cycle in the multiplexed mode. no wait state may be inserted if t he setup/hold time of the samp ling timing is not satisfied. the wait function is set to on or off by port mode control register cm (pmccm). (13) pcs0 to pcs7 (port cs) ? 3-state i/o pcs0 to pcs7 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as chip select signal out put in the control mode. (a) port mode pcs0 to pcs7 can be set in the input or output mode in 1-bit units, by using port mode register cs (pmcs). (b) control mode (i) cs0 to cs3 (chip select input) ? output these pins output a chip select signal to external memory and external peripheral i/o. the csn signal is assigned to memory block n (n = 0 to 3). this signal is asserted while a bus cycle for accessing the corresponding memory block is being executed. this signal is deasserted in the idle state (ti). chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 41 (14) pct0 to pct7 (port ct) ? 3-state i/o pct0 to pct7 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as control signal output in the control mode when memory is externally expanded. (a) port mode pct0 to pct7 can be set in the input or output mo de in 1-bit units, by using port mode register ct (pmct). (b) control mode (i) wr0 (lower byte write strobe) ? output this pin outputs the write strobe signal of th e lower data of the external 16-bit data bus. (ii) wr1 (upper byte write strobe) ? output this pin outputs the write strobe signal of th e higher data of the external 16-bit data bus. (iii) rd (read strobe) ? output this pin outputs the read strobe signal of the external 16-bit data bus. (iv) astb (address strobe) ? output this pin outputs the latch strobe signal of the extern al address bus. the signal output from this pin goes low at the falling edge of the t1 state of the bus cycle, and goes high at the falling edge of the t3 state. it goes high while the bus cycle is not active. (15) pdl0 to pdl15 (port dl) ? 3-state i/o pdl0 to pdl15 function as a 16-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as a time-division address/data bus (ad0 to ad15) when the memory is externally expanded. pdl5/ad5 also functions as the flmd1 pin when the flas h memory is programmed (when a high level is input to fld0). at this time, be sure to input a low level to the flmd1 pin. (a) port mode pdl0 to pdl15 can be set in the input or output mo de in 1-bit units, by using port mode register dl (pmdl). (b) control mode (i) ad0 to ad15 (address/data bus 0 to 15) ? 3-state i/o these are multiplexed address/data bus for external access. (16) reset (reset) ? input reset input is asynchronous input. when a signal wi th a fixed low level width is input to the reset pin regardless of the operating clock, the system is reset, taking precedenc e over all the other operations. this pin is used to release the standby mode (halt, idle , or stop), as well as for normal initialization/start. chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 42 (17) x1, x2 (crystal for main clock) these pins are used to connect the res onator that generates the system clock. (18) xt1, xt2 (crystal for subclock) these pins are used to connect the re sonator that generates the subclock. (19) av ss (ground for analog) this is a ground pin for the a/d converter and alternate-function ports. (20) av ref0 (analog reference voltage) ? input this pin supplies positive analog power to th e a/d converter and alternate-function ports. it also supplies a reference voltage to the a/d converter. (21) ev dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. (22) ev ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (23) v dd (power supply) this pin supplies positive power. connect all the v dd pins to a positive power supply. (24) v ss (ground) this is a ground pin. connect all the v ss pins to ground. (25) flmd0 (flash programming mode) ? input this is a signal input pin for flash memory programming mode. connect this pin to v ss in the normal operation mode. (26) bv dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. (27) bv ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (28) regc (regulator control) ? input this pin connects a capacitor for the regulator. chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 43 2.4 pin i/o circuit types and recomme nded connection of unused pins (1/3) pin i/o circuit type recommended connection p00/tip31/top31 p01/tip30/top30 p02/nmi p03/intp0/adtrg p04/intp1 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p05/intp2/drst 5-af input: independently connect to ev ss output: leave open p06/intp3 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p10/intp9 p11/intp10 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p30/txda0 5-a p31/rxda0/intp7 p32/ascka0/tip00/top00/ top01 p33/tip01/top01 p34/tip10/top10 p35/tip11/top11 5-w p36 p37 p38/txda2 5-a p39/rxda2/intp8 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p40/sib0 5-w p41/sob0 5-a p42/sckb0 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms 5-w p60/intp11 p61/intp12 p62/intp13 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 44 (2/3) pin i/o circuit type recommended connection p63 p64 p65 p66 p67 p68 p69 5-a p610/tiq20/toq20 p611/tiq21/toq21 p612/tiq22/toq22 p613/tiq23/toq23 5-w p614 p615 5-a input: independently connect to ev dd or ev ss via a resistor output: leave open p70/ani0 to p79/ani9 p710/ani10, p11/ani11 p712/ani12 to p715/ani15 11-g input: independently connect to av ref0 or av ss via a resistor output: leave open p80/rxda3 note /intp14 5-w p81/txda3 note 5-a input: independently connect to ev dd or ev ss via a resistor output: leave open p90/kr6/txda1 p91/kr7/rxda1 p92/tiq11/toq11 p93/tiq12/toq12 p94/tiq13/toq13 p95/tiq10/toq10 p96/tip21/top21 p97/sib1/tip20/top20 5-w p98/sob1 5-a p99/sckb1 p910/sib2 5-w p911/sob2 5-a p912/sckb2 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p913/intp4/pcl p914/intp5 p915/intp6 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p120/ani16 to p127/ani23 11-g input: independently connect to av ref0 or av ss via a resistor output: leave open pcd0 to pcd3 5 input: independently connect to bv dd or bv ss via a resistor output: leave open note pd70f3711, 70f3712 only chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 45 (3/3) pin i/o circuit type recommended connection pcm0/wait pcm1/clkout pcm2/hldak pcm3/hldrq pcm4 pcm5 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pcs0/cs0, pcs1/cs1 pcs2/cs2, pcs3/cs3, pcs4 to pcs7 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pct0/wr0 pct1/wr1 pct2 pct3 pct4/rd pct5 pct6/astb pct7 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pdl0/ad0 to pdl4/ad4 pdl5/ad5/flmd1 pdl6/ad6, pdl7/ad7 pdl8/ad8 to pdl11/ad11 pdl12/ad12, pdl13/ad13 pdl14/ad14, pdl15/ad15 5 input: independently connect to bv dd or bv ss via a resistor output: leave open av ref0 ? directly connect to v dd av ss ? ? flmd0 note ? directly connect to v ss regc ? ? reset 2 ? x1 ? ? x2 ? ? xt1 16 connect to v ss via a resistor xt2 16 leave open v dd ? ? v ss ? ? bv dd ? ? bv ss ? ? ev dd ? ? ev ss ? ? note if noise that exceeds the noise elimination width is input to the reset pin during self programming, the flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is connected to the flmd0 pin. therefore, do not connect a capacitor to the flmd0 pin. chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 46 2.5 pin i/o circuits figure 2-1. pin i/o circuit types (1/2) in data output disable p-ch in/out v dd n-ch input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch v ref (threshold voltage) comparator schmitt-triggered input with hysteresis characteristics input enable + _ av ss av ss pull-up enable pull-down enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch n -ch type 2 type 5-af type 5 type 11-g chapter 2 pin functions preliminary user?s manual u17717ej2v0ud 47 figure 2-1. pin i/o circuit types (2/2) data output disable p-ch in/out v dd n-ch input enable p-ch v dd pull-up enable pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch p-ch feedback cut-off xt1 xt2 type 5-a type 5-w type 16 2.6 cautions note that the following pin may tempor arily output an undefined level, even during reset upon power application. p53/kr3/tiq00/ toq00/ddo pin preliminary user?s manual u17717ej2v0ud 48 chapter 3 cpu function the cpu of the v850es/hj2 is based on ri sc architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 50 ns (at 20 mhz operation) memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 49 3.2 cpu register set the registers of the v850e s/hj2 can be classified into two types : general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 50 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these inst ructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that i ndicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution remark for furthers details on the r1, r3 to r5, and r31 that are used in the assembler and c compiler, refer to the ca850 (c compiler package) as sembly language user?s manual . (2) program counter (pc) the program counter holds the instructi on address during program execution. the lower 26 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 51 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/sto re instructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of these registers is availa ble, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during the interval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. caution even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt ser vicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 52 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, th e contents of the program counter (pc) are saved to eipc, and the contents of the program status word ( psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and f epsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions (see 16.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). the value of eipc is restored to the pc and the val ue of eipsw to the psw by the reti instruction. 31 0 eipc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 53 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under exec ution, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is avai lable, the contents of thes e registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). the value of fepc is restored to the pc and the value of fepsw to the psw by the reti instruction. 31 0 fepc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) hol ds the source of an exception or in terrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt source. because this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 54 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate th e status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this regi ster are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instructi on execution. however if the id flag is set to 1, interrupt requests will not be acknowledged while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being proces sed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page. chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 55 (2/2) note the result of the operation that has performed satura tion processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execut ion status saving registers. when the callt instruction is execut ed, the contents of the program co unter (pc) are saved to ctpc, and those of the program status wo rd (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 56 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of th e instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. this register can be read or written only during the in terval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). the value of dbpc is restored to the pc and the value of dbpsw to the psw by the dbret instruction. 31 0 dbpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a tabl e address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 57 3.3 operation modes the v850es/hj2 has the following operation modes. (1) normal operation mode in this mode, each pin related to the bus interface is set to the port mode after system reset has been released. execution branches to the reset entry address of the intern al rom, and then instruction processing is started. (2) flash memory programming mode in this mode, the internal flash memory can be programmed by using a flash programmer. (3) on-chip debug mode the v850es/hj2 is provided with an on -chip debug function that employs t he jtag (joint test action group) communication specifications and that is executed via an on-chip debug emulator. for details, see chapter 26 on-chip debug function . 3.3.1 specifying operation mode specify the operation mode by using the flmd0 and flmd1 pins. in the normal mode, input a low level to the flmd0 pin when reset is released. in the flash memory programming mode, a high level is input to the flmd0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. operation when reset is released flmd0 flmd1 operation mode after reset l normal operation mode h l flash memory programming mode h h setting prohibited remark l: low-level input h: high-level input : don?t care chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 58 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 16 mb of external memory area and internal rom area, plus an internal ram area, are supported in a linear addres s space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear address s pace (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical address space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. image on address space program space internal ram area use-prohibited area use-prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 peripheral i/o area internal ram area use-prohibited area external memory area internal rom area (external memory area) 16 mb 4 gb 64 mb 64 mb chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 59 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the highest address of the program space, 03ffffffh, and t he lowest address, 00000000h, are contiguous addresses. that the highest address and the lowest address of the program space are contiguous in this way is called wraparound. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetc hed from this area. therefore , do not execute an operation in which the result of a branch addr ess calculation affects this area. program space program space (+) direction ( ? ) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and the lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 60 3.4.3 memory map the areas shown below are reserved in the v850es/hj2. figure 3-2. data memory map (physical addresses) (2 mb) (80 kb) use prohibited external memory area (64 kb) use prohibited use prohibited internal rom area note 2 (1 mb) use prohibited external memory area (64 kb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use prohibited note 1 03ffffffh 03fec000h 00810000h 0080ffffh external memory area (64 kb) 00410000h 0040ffffh external memory area (64 kb) 00210000h 0020ffffh 008000000h 007ffffffh 00400000h 003fffffh 00200000h 001fffffh 00000000h 03febfffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh use prohibited 03fef000h 03feefffh 03fec000h 001fffffh 00100000h 000fffffh 00110000h 0010ffffh 00000000h notes 1. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. fetch access and read access to addresses 00000000h to 000fffffh is made to the internal rom area. however, data write access to these addresses is made to the external memory area. chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 61 figure 3-3. program memory map internal ram area (60 kb) note use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (14 mb) external memory area (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h note for details, see 3.4.4 (2) internal ram area . chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 62 3.4.4 areas (1) internal rom area up to 1 mb is reserved as an internal rom area. (a) internal rom (128 kb) 128 kb are allocated to addresse s 0000000h to 001ffffh in the pd70f3709. accessing addresses 0020000h to 00fffffh is prohibited. figure 3-4. internal rom area (128 kb) 00fffffh 0020000h 001ffffh 0000000h access-prohibited area internal rom area (128 kb) (b) internal rom (256 kb) 256 kb are allocated to addresses 00000000h to 0003ffffh in the pd70f3710. accessing addresses 00040000h to 000fffffh is prohibited. figure 3-5. internal rom area (256 kb) access-prohibited area internal rom area (256 kb) 0040000h 00fffffh 003ffffh 0000000h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 63 (c) internal rom (376 kb) 376 kb are allocated to addresses 00000000h to 0005dfffh in the pd70f3711. accessing addresses 0005e000h to 000fffffh is prohibited. figure 3-6. internal rom area (376 kb) access-prohibited area internal rom (376 kb) 0005e000h 0005dfffh 00000000h 000fffffh (d) internal rom (512 kb) 512 kb are allocated to addresses 00000000h to 0007ffffh in the pd70f3712. accessing addresses 00080000h to 000fffffh is prohibited. figure 3-7. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 00080000h 0007ffffh 00000000h 000fffffh chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 64 (2) internal ram area up to 60 kb are reserved as the internal ram area. (a) internal ram (12 kb) 12 kb are allocated to addresses 03ffc000h to 03ffefffh in the following versions. accessing addresses 03ff0000h to 03ffbfffh is prohibited. ? pd70f3709, 70f3710 figure 3-8. internal ram area (12 kb) access-prohibited area internal ram 03ff0000h 03ffefffh 03ffc000h 03ffbfffh ffffc000h ffffbfffh ffff0000h ffffefffh physical address space logical address space (b) internal ram (20 kb) 20 kb are allocated to addresses 03ffa000h to 03ffefffh in the following versions. accessing addresses 03ff0000h to 03ff9fffh is prohibited. ? pd70f3711, 70f3712 figure 3-9. internal ram area (20 kb) access-prohibited area internal ram 03ff0000h 03ffefffh 03ffa000h 03ff9fffh ffffa000h ffff9fffh ffff0000h ffffefffh physical address space logical address space chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 65 (3) on-chip peripheral i/o area 4 kb of addresses 03fff000h to 03ffffffh are re served as the on-chip peripheral i/o area. figure 3-10. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 03ffffffh 03fff000h ffffffffh fffff000h physical address space logical address space peripheral i/o registers that have functions to specif y the operation mode for and mo nitor the status of the on- chip peripheral i/o are mapped to the on-chip periphe ral i/o area. program cannot be fetched from this area. cautions 1. when a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read , and data is written to the lower 8 bits. 3. addresses not defined as registers are r eserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. (4) external memory area 256 kb are allocated as the external memory area. for details, see chapter 5 bus control function . chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 66 3.4.5 recommended use of address space the architecture of the v850es/hj2 re quires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. beca use the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the pe rformance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program counte r), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb spac e of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program space, access following addresses. caution if a branch instruction is at the upper limi t of the internal ram ar ea, a prefetch operation (invalid fetch) straddling the on-chip peripheral i/o area does not occur. ram size access address 20 kb 03ffa000h to 03ffefffh 12 kb 03ffc000h to 03ffefffh chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 67 (2) data space with the v850es/hj2, it seems that there are sixty-four 64 mb addr ess spaces on the 4 gb cpu address space. therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically eliminates the need for registers dedicated to pointers. figure 3-11. wraparound ( pd70f3712) access-prohibited area 8 kb internal rom area on-chip peripheral i/o area internal ram area 3 2 kb 4 kb 20 kb (r = ) 0005ffffh 00007fffh 00000000h fffff000h ffffefffh ffffa000h ffff9fffh ffff8000h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 68 figure 3-12. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffa000h 03ff9fffh 03ff0000h 03feffffh 01000000h 00ffffffh 00080000h 0007ffffh 00100000h 000fffffh 00000000h ffffffffh fffff000h ffffefffh ffffa000h ffff9fffh ffff0000h fffeffffh 00100000h 000fffffh 00000000h use prohibited remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd70f3712. chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 69 3.4.6 peripheral i/o registers (1/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl pdl undefined fffff004h port dll pdll undefined fffff005h port dlh pdlh undefined fffff008h port cs pcs undefined fffff00ah port ct pct undefined fffff00ch port cm pcm undefined fffff00eh port cd pcd undefined fffff024h port mode register dl pmdl ffffh fffff024h port mode register dll pmdll ffh fffff025h port mode register dlh pmdlh ffh fffff028h port mode register cs pmcs ffh fffff02ah port mode register ct pmct ffh fffff02ch port mode register cm pmcm ffh fffff02eh port mode register cd pmcd ffh fffff044h port mode control register dl pmcdl 0000h fffff044h port mode control register dll pmcdll 00h fffff045h port mode control register dlh pmcdlh 00h fffff048h port mode control register cs pmccs 00h fffff04ah port mode control register ct pmcct 00h fffff04ch port mode control register cm pmccm 00h fffff066h bus size configur ation register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 70 (2/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h ffh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 r/w 47h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 71 (3/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 47h fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tm0eqic0 47h fffff146h interrupt control register cb0ric 47h fffff148h interrupt control register cb0tic 47h fffff14ah interrupt control register cb1ric 47h fffff14ch interrupt control register cb1tic 47h fffff14eh interrupt control register ua0ric 47h fffff150h interrupt control register ua0tic 47h fffff152h interrupt control register ua1ric 47h fffff154h interrupt control register ua1tic 47h fffff156h interrupt control register adic 47h fffff160h interrupt control register kric 47h fffff162h interrupt control register wtiic 47h fffff164h interrupt control register wtic 47h fffff166h interrupt control register pic8 47h fffff168h interrupt control register pic9 47h fffff16ah interrupt control register pic10 47h fffff16ch interrupt control register tq1ovic 47h fffff16eh interrupt control register tq1ccic0 47h fffff170h interrupt control register tq1ccic1 47h fffff172h interrupt control register tq1ccic2 47h fffff174h interrupt control register tq1ccic3 47h fffff176h interrupt control register ua2ric 47h fffff178h interrupt control register ua2tic 47h fffff182h interrupt control register dmaic0 47h fffff184h interrupt control register dmaic1 47h fffff186h interrupt control register dmaic2 47h fffff188h interrupt control register dmaic3 47h fffff18ah interrupt control register pic11 47h fffff18ch interrupt control register pic12 47h fffff18eh interrupt control register pic13 47h fffff190h interrupt control register pic14 47h fffff192h interrupt control register tq2ovic 47h fffff194h interrupt control register tq2ccic0 47h fffff196h interrupt control register tq2ccic1 47h fffff198h interrupt control register tq2ccic2 r/w 47h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 72 (4/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff19ah interrupt control register tq2ccic3 47h fffff19ch interrupt control register cb2ric 47h fffff19eh interrupt control register cb2tic 47h fffff1a0h interrupt control register ua3ric note 47h fffff1a2h interrupt control register ua3tic note r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail comparison mode register ada0pfm 00h fffff205h power-fail comparison threshold value register ada0pft r/w 00h fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h undefined fffff224h a/d conversion result register 10 ada0cr10 undefined fffff225h a/d conversion result register 10h ada0cr10h undefined fffff226h a/d conversion result register 11 ada0cr11 undefined fffff227h a/d conversion result register 11h ada0cr11h undefined fffff228h a/d conversion result register 12 ada0cr12 undefined fffff229h a/d conversion result register 12h ada0cr12h r undefined note pd70f3711, 70f3712 only chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 73 (5/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff22ah a/d conversion result register 13 ada0cr13 undefined fffff22bh a/d conversion result register 13h ada0cr13h undefined fffff22ch a/d conversion result register 14 ada0cr14 undefined fffff22dh a/d conversion result register 14h ada0cr14h undefined fffff22eh a/d conversion result register 15 ada0cr15 undefined fffff22fh a/d conversion result register 15h ada0cr15h undefined fffff230h a/d conversion result register 16 ada0cr16 undefined fffff231h a/d conversion result register 16h ada0cr16h undefined fffff232h a/d conversion result register 17 ada0cr17 undefined fffff233h a/d conversion result register 17h ada0cr17h undefined fffff234h a/d conversion result register 18 ada0cr18 undefined fffff235h a/d conversion result register 18h ada0cr18h undefined fffff236h a/d conversion result register 19 ada0cr19 undefined fffff237h a/d conversion result register 19h ada0cr19h undefined fffff238h a/d conversion result register 20 ada0cr20 undefined fffff239h a/d conversion result register 20h ada0cr20h undefined fffff23ah a/d conversion result register 21 ada0cr21 undefined fffff23bh a/d conversion result register 21h ada0cr21h undefined fffff23ch a/d conversion result register 22 ada0cr22 undefined fffff23dh a/d conversion result register 22h ada0cr22h undefined fffff23eh a/d conversion result register 23 ada0cr23 undefined fffff23fh a/d conversion result register 23h ada0cr23h r undefined fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff318h noise elimination control register nfc 00h fffff400h port 0 p0 undefined fffff402h port 1 p1 undefined fffff406h port 3 p3 undefined fffff406h port 3l p3l undefined fffff407h port 3h p3h undefined fffff408h port 4 p4 undefined fffff40ah port 5 p5 undefined fffff40ch port 6 p6 undefined fffff40ch port 6l p6l undefined fffff40dh port 6h p6h undefined fffff40eh port 7l p7l undefined fffff40fh port 7h p7h undefined fffff410h port 8 p8 undefined fffff412h port 9 p9 undefined fffff412h port 9l p9l undefined fffff413h port 9h p9h undefined fffff418h port 12 p12 r/w undefined chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 74 (6/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff420h port mode register 0 pm0 ffh fffff422h port mode register 1 pm1 ffh fffff426h port mode register 3 pm3 ffffh fffff426h port mode register 3l pm3l ffh fffff427h port mode register 3h pm3h ffh fffff428h port mode register 4 pm4 ffh fffff42ah port mode register 5 pm5 ffh fffff42ch port mode register 6 pm6 ffffh fffff42ch port mode register 6l pm6l ffh fffff42dh port mode register 6h pm6h ffh fffff42eh port mode register 7l pm7l ffh fffff42fh port mode register 7h pm7h ffh fffff430h port mode register 8 pm8 ffh fffff432h port mode register 9 pm9 ffffh fffff432h port mode register 9l pm9l ffh fffff433h port mode register 9h pm9h ffh fffff438h port mode register 12 pm12 ffh fffff440h port mode control register 0 pmc0 00h fffff442h port mode control register 1 pmc1 00h fffff446h port mode control register 3 pmc3 0000h fffff446h port mode control register 3l pmc3l 00h fffff447h port mode control register 3h pmc3h 00h fffff448h port mode control register 4 pmc4 00h fffff44ah port mode control register 5 pmc5 00h fffff44ch port mode control register 6 pmc6 0000h fffff44ch port mode control register 6l pmc6l 00h fffff44dh port mode control register 6h pmc6h 00h fffff450h port mode control register 8 pmc8 00h fffff452h port mode control register 9 pmc9 0000h fffff452h port mode control register 9l pmc9l 00h fffff453h port mode control register 9h pmc9h 00h fffff460h port function control register 0 pfc0 00h fffff466h port function control register 3l pfc3l 00h fffff46ah port function control register 5 pfc5 00h fffff46ch port function control register 6 pfc6 0000h fffff46ch port function control register 6l pfc6l 00h fffff46dh port function control register 6h pfc6h 00h fffff472h port function control register 9 pfc9 0000h fffff472h port function control register 9l pfc9l 00h fffff473h port function control register 9h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc r/w ffffh chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 75 (7/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 00h fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp2 control register 0 tp3ctl0 00h fffff5c1h tmp2 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 r/w 00h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 76 (8/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff610h tmq1 control register 0 tq1ctl0 00h fffff611h tmq1 control register 1 tq1ctl1 00h fffff612h tmq1 i/o control register 0 tq1ioc0 00h fffff613h tmq1 i/o control register 1 tq1ioc1 00h fffff614h tmq1 i/o control register 2 tq1ioc2 00h fffff615h tmq1 timer option register 0 tq1opt0 00h fffff616h tmq1 capture/compare register 0 tq1ccr0 0000h fffff618h tmq1 capture/compare register 1 tq1ccr1 0000h fffff61ah tmq1 capture/compare register 2 tq1ccr2 0000h fffff61ch tmq1 capture/compare register 3 tq1ccr3 r/w 0000h fffff61eh tmq1 counter read buffer register tq1cnt r 0000h fffff620h tmq2 control register 0 tq2ctl0 00h fffff621h tmq2 control register 1 tq2ctl1 00h fffff622h tmq2 i/o control register 0 tq2ioc0 00h fffff623h tmq2 i/o control register 1 tq2ioc1 00h fffff624h tmq2 i/o control register 2 tq2ioc2 00h fffff625h tmq2 timer option register 0 tq2opt0 00h fffff626h tmq2 capture/compare register 0 tq2ccr0 0000h fffff628h tmq2 capture/compare register 1 tq2ccr1 0000h fffff62ah tmq2 capture/compare register 2 tq2ccr2 0000h fffff62ch tmq2 capture/compare register 3 tq2ccr3 r/w 0000h fffff62eh tmq2 counter read buffer register tq2cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff706h port function control expansion register 3l pfce3l 00h fffff70ah port function control expansion register 5 pfce5 00h fffff712h port function control expansion register 9 pfce9 0000h fffff712h port function control expansion register 9l pfce9l 00h fffff713h port function control expansion register 9h pfce9h 00h fffff802h system status register sys 00h fffff80ch internal oscillation mode register rcm r/w 00h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 77 (9/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff810h dma trigger source register 0 dtfr0 00h fffff812h dma trigger source register 1 dtfr1 00h fffff814h dma trigger source register 2 dtfr2 00h fffff816h dma trigger source register 3 dtfr3 00h fffff820h power save mode register psmr r/w 00h fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operating clock status register ccls r 00h fffff82fh programmable clock mode register pclm 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emulat ion register 1 pemu1 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 receive data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx r/w ffh caution for details of the ocdm regist er, see chapter 26 on-chip debug function. chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 78 (10/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffa30h uarta3 control register 0 ua3ctl0 note 10h fffffa31h uarta3 control register 1 ua3ctl1 note 00h fffffa32h uarta3 control register 2 ua3ctl2 note ffh fffffa33h uarta3 option control register 0 ua3opt0 note 14h fffffa34h uarta3 status register ua3str note r/w 00h fffffa36h uarta3 receive data register ua3rx note r ffh fffffa37h uarta3 transmit data register ua3tx note ffh fffffb00h tip00 pin noise eliminat ion control register p00nfc 00h fffffb04h tip01 pin noise eliminat ion control register p01nfc 00h fffffb08h tip10 pin noise eliminat ion control register p10nfc 00h fffffb0ch tip11 pin noise eliminat ion control register p11nfc 00h fffffb10h tip20 pin noise eliminat ion control register p20nfc 00h fffffb14h tip21 pin noise eliminat ion control register p21nfc 00h fffffb18h tip30 pin noise eliminat ion control register p30nfc 00h fffffb1ch tip31 pin noise eliminat ion control register p31nfc 00h fffffb50h tiq00 pin noise eliminat ion control register q00nfc 00h fffffb54h tiq01 pin noise eliminat ion control register q01nfc 00h fffffb58h tiq02 pin noise eliminat ion control register q02nfc 00h fffffb5ch tiq03 pin noise eliminat ion control register q03nfc 00h fffffb60h tiq10 pin noise eliminat ion control register q10nfc 00h fffffb64h tiq11 pin noise eliminat ion control register q11nfc 00h fffffb68h tiq12 pin noise eliminat ion control register q12nfc 00h fffffb6ch tiq13 pin noise eliminat ion control register q13nfc 00h fffffb70h tiq20 pin noise eliminat ion control register q20nfc 00h fffffb74h tiq21 pin noise eliminat ion control register q21nfc 00h fffffb78h tiq22 pin noise eliminat ion control register q22nfc 00h fffffb7ch tiq23 pin noise eliminat ion control register q23nfc 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc02h external interrupt falling edge specification register 1 intf1 00h fffffc06h external interrupt falling edge specification register 3 intf3 0000h fffffc06h external interrupt falling edge specification register 3l intf3l 00h fffffc07h external interrupt falling edge specification register 3h intf3h 00h fffffc0ch external interrupt falling edge specification register 6l intf6l 00h fffffc10h external interrupt falling edge specification register 8 intf8 00h fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc22h external interrupt rising edge specification register 1 intr1 r/w 00h note pd70f3711, 70f3712 only chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 79 (11/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc26h external interrupt rising edge specification register 3 intr3 0000h fffffc26h external interrupt rising edge specification register 3l intr3l 00h fffffc27h external interrupt rising edge specification register 3h intr3h 00h fffffc2ch external interrupt rising edge specification register 6l intr6l 00h fffffc30h external interrupt rising edge specification register 8 intr8 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc40h pull-up resistor option register 0 pu0 00h fffffc42h pull-up resistor option register 1 pu1 00h fffffc46h pull-up resistor option register 3 pu3 0000h fffffc46h pull-up resistor option register 3l pu3l 00h fffffc47h pull-up resistor option register 3h pu3h 00h fffffc48h pull-up resistor option register 4 pu4 00h fffffc4ah pull-up resistor option register 5 pu5 00h fffffc4ch pull-up resistor option register 6 pu6 0000h fffffc4ch pull-up resistor option register 6l pu6l 00h fffffc4dh pull-up resistor option register 6h pu6h 00h fffffc50h pull-up resistor option register 8 pu8 00h fffffc52h pull-up resistor option register 9 pu9 0000h fffffc52h pull-up resistor option register 9l pu9l 00h fffffc53h pull-up resistor option register 9h pu9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1 control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl r/w 00h chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 80 3.4.7 special registers special registers are registers that are protected from being written with illegal data due to a program hang-up. v850es/hj2 has the following seven special registers. ? power save control register (psc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? internal ram data status register (rams) ? on-chip debug mode register (ocdm) in addition, the prcdm register is provided to protect again st a write access to the spec ial registers so that the application system does not inadvertently stop due to a progra m hang-up. a write access to the special registers is made in a specific sequence, and an illegal st ore operation is reported to the sys register. chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 81 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the prcmd register. <4> write the setting data to the special regi ster (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<5> to <9> insert nop instructions (5 instructions).) note <10> enable dma operation if necessary. [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop note ; dummy instruction <6>nop note ; dummy instruction <7>nop note ; dummy instruction <8>nop note ; dummy instruction <9>nop note ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence to read a special register. note five nop instructions or more must be inserted immediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). cautions 1. when a store instruction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the speci al register (<4> in example) to write data to the prcmd register (<3> in example). the same applies when a general-purpose register is used for addressing. chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 82 (2) command register (prcmd) the prcmd register is an 8-bit regist er that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. the first write access to a special register is valid after data has be en written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 83 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 protection error did not occur protection error occurred prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <4> is executed without executing <3> in 3.4.7 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a special register (including execution of a bit manipulation instruction) afte r writing data to the prcmd register (if <4> in 3.4.7 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is read (except by a bit manipulation instruction) between an operation to write the prcmd register and an operation to write a special register, the prerr flag is not set, and the set dat a can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcm d register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd regist er, which is not a special register, immediately after a write access to the prcmd regi ster, the prerr bit is set to 1. chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 84 3.4.8 cautions (1) registers to be set first be sure to set the following registers first when using the v850es/hj2. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) after setting the vswc, ocdm, and wdtm2 registers, set the other registers as necessary. when using the external bus, set each pin to the alternate-function bus control pin mode by using the port- related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls wait of bus a ccess to the on-chip peripheral i/o registers. three clocks are required to access an on-chip per ipheral i/o register (without a wait cycle). the v850es/hj2 requires wait cycles according to the oper ating frequency. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 16.6 mhz f clk 20 mhz 01h 1 (b) on-chip debug mode register (ocdm) for details, see chapter 26 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time a nd the operation clock of watchdog timer 2. watchdog timer 2 automatically starts in the reset mode after reset is released. write the wdtm2 register to activate this operation. for details, see chapter 11 functions of watchdog timer 2 . chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 85 (2) accessing specific on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the cloc k of the peripheral bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. if there is a possibility of a conflict, the number of cycles for acce ssing the cpu changes when t he peripheral hardware is accessed, so that correct data is transferred. as a re sult, the cpu does not start processing of the next instruction but enters the wait state. if this wait st ate occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when specific on-chip peripheral i/o r egisters are accessed, more wait stat es may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. peripheral function register name access k tpncnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter p (tmp) (n = 0 to 3) tpnccr0, tpnccr1 read 1 or 2 tqmcnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter q (tmq) (m = 0 to 2) tqmccr0 to tqmccr3 read 1 or 2 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 ada0m0 read 1 or 2 ada0cr0 to ada0cr23 read 1 or 2 a/d converter ada0cr0h to ada0cr23h read 1 or 2 number of clocks necessary for access = 3 + i + j + (2 + j) k caution accessing the above register s is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock remark i: values (0 or 1) of higher 4 bits of vswc register j: values (0 or 1) of lower 4 bits of vswc register chapter 3 cpu function preliminary user?s manual u17717ej2v0ud 86 (3) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 preliminary user?s manual u17717ej2v0ud 87 chapter 4 port functions 4.1 features o i/o ports: 128 o port pins function alternately as other peripheral-function i/o pins o can be set in input or output mode in 1-bit units. 4.2 basic configuration of ports the v850es/hj2 has a total of 128 i/o ports, ports 0, 1, 3 to 9, 12, cd, cm, cs, ct, and dl. the port configuration is shown below. figure 4-1. port configuration p00 p06 port 0 pcd0 pcd3 port cd pcm0 pcm5 port cm pcs0 pcs7 pct0 pct7 port cs port ct p90 p915 port 9 p120 p127 port 12 pdl0 pdl15 port dl p30 p39 port 3 port 1 p40 p42 port 4 p50 p55 port 5 p60 p615 p70 p715 p80 p81 port 6 p10 p11 port 7 port 8 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 88 table 4-1. configuration of ports item configuration port mode register (pmn: n = 0, 1, 3, 4, 5, 6, 7l, 7h, 8, 9, 12, cd, cm, cs, ct, or dl) port mode control register (pmcn: n = 0, 1, 3, 4, 5, 6, 8, 9, cd, cm, cs, ct, or dl) port function control register (pfcn: n = 0, 3l, 5, 6, or 9) port function control expansion register (pfcen: n = 3l, 5, or 9) control registers pull-up resistor option register (pun: n = 0, 1, 3, 4, 5, 6, 8, or 9) ports 128 table 4-2. pin i/o buffer power supplies power supply corresponding pin av ref0 port 7, port 12 bv dd port cd, port cm, port cs, port ct, port dl ev dd port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9, reset chapter 4 port functions preliminary user?s manual u17717ej2v0ud 89 4.3 port functions 4.3.1 operation of port function the operation of a port differs depending on setting of the input or output mode, as follows. (1) writing to i/o port (a) in output mode a value can be written to the output latch by using a transfer instruction. the contents of the output latch are output from the pin. once dat a has been written to the output latch, it is retained until new data is written to the output latch. (b) in input mode a value can be written to the output latch by using a trans fer instruction. because t he output buffer is off, however, the status of the pin remains unchanged. once data has been written to the output latch, it is retained until new data is wri tten to the output latch. caution although a 1-bit memory manipulation instruction manipul ates 1 bit, it accesses a port in 8-bit units. if a port has a mixture of input a nd output pins, therefore, the contents of the output latch of a pin set in the input mode become undefined, even if the pin is not subject to manipulation. (2) reading from i/o port (a) in output mode the contents of the out put latch can be read by using a transfer in struction. the cont ents of the output latch are not changed. (b) in input mode the status of the pin can be read by using a transfer instruction. the contents of the out put latch are not changed. (3) operation of i/o port (a) in output mode an operation is performed on the cont ents of the output latch and the result is written to the output latch. the contents of the output latc h are output from the pin. once data has been written to the output latch, it is retained until new data is wri tten to the output latch. (b) in input mode the contents of the output latch become undefined. because the output buffer is off, however, the status of the pin remains unchanged. caution although a 1-bit memory manipulation instruction manipul ates 1 bit, it accesses a port in 8-bit units. if a port has a mixture of input a nd output pins, therefore, the contents of the output latch of a pin set in the input mode become undefined, even if the pin is not subject to manipulation. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 90 4.3.2 notes on setting port pins (1) the number of ports and alternate functions differs depe nding on the product. set the registers related to the unavailable ports and alternate functions to the value after reset. (2) set the registers of the por ts using the following procedure. <1> set port function control register n (pfcn) and port function control expansion register n (pfcen). <2> set port mode control register n (pmcn). <3> set external interrupt falling edge specification register n (intfn) and external interrupt rising edge specification register n (intrn). if the pfcn and pfcen registers are se t after the pmcn register was set, an unexpected peripheral function pin may be set while the pfcn and pfcen registers are being set. (3) the punm bit (which connects an on-chip pull-up resisto r) of the pun register is valid only in the input mode (pmnm bit of pmn register = 1). in the output mode (pmnm bit of pmn register = 0), the on-chip pull-up register is disconnected by hardware. (4) reading the pin level and port latch is controlled by the port mode register (pmn). the same applies when an alternate function is used. (5) the schmitt (shmt)-trigger input buffer does not operate as an shmt buffer when it is read in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 91 4.3.3 port 0 port 0 is a 7-bit port (p00 to p06) for whic h i/o settings can be controlled in 1-bit units. (1) functions of port 0 ? the input/output data of the port can be specified in 1-bit units. specified by port register 0 (p0) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 0 (pm0) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 0 (pmc0) ? control mode 1 or control mode 2 can be specified in 1-bit units. specified by port function control register 0 (pfc0) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 0 (pu0) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 0 (intf0) and external interrupt rising edge specification register 0 (intr0) port 0 functions alternately as the following pins. table 4-3. alternate-function pins of port 0 pin name alternate-function pin name i/o remark block type p00 tp31/top31 g-1 p01 tp30/top30 g-1 p02 nmi note 1 l-1 p03 intp0/adtrg n-1 p04 intp1 l-1 p05 intp2/drst note 2 aa-1 port 0 p06 intp3 i/o ? l-1 notes 1. the nmi pin alternately functions as the p02 pi n. it functions as the p02 pin after reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using intf0 and intr0 registers. 2. the alternate function of the p05 pin is the on- chip debug function. a fter external reset, the p05/intp2/drst pin is initialized as the on-chip debug pin (drst). to use the p05 pin as a port pin, not as an on-chip debug pin, the following actions must be taken. <1> clear the ocdm0 bit of the ocdm register (special register) to 0. <2> fix the p05/intp2/drst pin to the low level until the above action has been taken. when the on-chip debug function is not used, i nputting a high level to the drst pin before the above actions are taken may cause a malfunction (cpu deadlock). exercise utmost care in handling the p05 pin. when a high level is not input to the p05/intp2/drst pin (when this pin is fixed to low level), it is not necessary to manipulate the o cdm0 bit of the ocdm register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 92 because a pull-down resistor (30 k ? typ) is connected to the buffer of the p05/intp2/drst pin, the pin does not have to be fixed to the low level by an external source. the pull-down resistor is disconnected by clearing the ocdm0 bit to 0. caution the p00 to p06 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hyster esis characteristics in the port mode. (2) registers (a) port register 0 (p0) port register 0 (p0) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff400h 7 6 5 4 3 2 1 0 p0 0 p06 p05 p04 p03 p02 p01 p00 p0n control of output data (in output mode) (n = 0 to 6) 0 output 0. 1 output 1. (b) port mode register 0 (pm0) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff420h 7 6 5 4 3 2 1 0 pm0 1 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n control of input/output mode (n = 0 to 6) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 93 (c) port mode control register 0 (pmc0) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff440h 7 6 5 4 3 2 1 0 pmc0 0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 pmc06 specification of operation mode of p06 pin 0 i/o port 1 intp3 input pmc05 specification of operation mode of p05 pin 0 i/o port 1 intp2/drst input pmc04 specification of operation mode of p04 pin 0 i/o port 1 intp1 input pmc03 specification of operation mode of p03 pin 0 i/o port 1 intp0/adtrg input pmc02 specification of operation mode of p02 pin 0 i/o port 1 nmi input pmc01 specification of operation mode of p01 pin 0 i/o port 1 tip30/top30 i/o pmc00 specification of operation mode of p00 pin 0 i/o port 1 tip31/top31 i/o caution the p05/intp2/drst pin functions as th e drst pin when the ocdm.ocdm0 bit is 1, regardless of the value of the pmc05 bit. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 94 (d) port function control register 0 (pfc0) this is an 8-bit register that specifies control mode 1 or control mode 2. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff460h 7 6 5 4 3 2 1 0 pfc0 0 0 0 0 pfc03 0 pfc01 pfc00 pfc03 specification of operation mode when p03 pin is in control mode 0 intp0 input 1 adtrg input pfc01 specification of operation mode when p01 pin is in control mode 0 tip30 input 1 top30 output pfc00 specification of operation mode when p00 pin is in control mode 0 tip31 input 1 top31 output (e) pull-up resistor option register 0 (pu0) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc40h 7 6 5 4 3 2 1 0 pu0 0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 pu0n control of on-chip pull-up resistor connection (n = 0 to 6) 0 not connected 1 connected chapter 4 port functions preliminary user?s manual u17717ej2v0ud 95 (f) external interrupt falling edge specification register 0 (intf0) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf0n and intr0n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. 3. for how to set the intern al noise filter (analog delay/digital delay) of intp3, see chapter 16 interrupt/exception processing function. after reset: 00h r/w address: fffffc00h 7 6 5 4 3 2 1 0 intf0 0 intf06 intf05 intf04 intf03 intf02 0 0 remark see table 4-4 for how to specify a valid edge. (g) external interrupt rising edge specification register 0 (intr0) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf0n and intr0n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. 3. for how to set the intern al noise filter (analog delay/digital delay) of intp3, see chapter 16 interrupt/exception processing function. after reset: 00h r/w address: fffffc20h 7 6 5 4 3 2 1 0 intr0 0 intr06 intr05 intr04 intr03 intr02 0 0 remark see table 4-4 for how to specify a valid edge. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 96 table 4-4. valid edge specification intf0n bit intr0n bit valid edge specification (n = 2 to 6) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2: control of nmi pin n = 3: control of intp0 pin n = 4: control of intp1 pin n = 5: control of intp2 pin n = 6: control of intp3 pin chapter 4 port functions preliminary user?s manual u17717ej2v0ud 97 4.3.4 port 1 port 1 is a 2-bit port (p10, p11) for which i/o settings can be controlled in 1-bit units. (1) functions of port 1 o the input/output data of the port can be specified in 1-bit units. specified by port register 1 (p1) o the input/output mode of the port can be specified in 1-bit units. specified by port mode register 1 (pm1) o port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 1 (pmc1) o an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 1 (pu1) o the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 1 (intf1) and external interrupt rising edge specification register 1 (intr1) port 1 functions alternately as the following pins. table 4-5. alternate-function pins of port 1 pin name alternate-function pin name i/o remark block type p10 intp9 l-1 port 1 p11 intp10 i/o ? l-1 caution the p10 and p11 pins have hysteresis char acteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 98 (2) registers (a) port register 1 (p1) port register 1 (p1) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff402h 7 6 5 4 3 2 1 0 p1 0 0 0 0 0 0 p11 p10 p1n control of output data (in output mode) (n = 0, 1) 0 output 0. 1 output 1. (b) port mode register 1 (pm1) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff422h 7 6 5 4 3 2 1 0 pm1 1 1 1 1 1 1 pm11 pm10 pm1n control of input/output mode (n = 0, 1) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 99 (c) port mode control register 1 (pmc1) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff442h 7 6 5 4 3 2 1 0 pmc1 0 0 0 0 0 0 pmc11 pmc10 pmc11 specification of operation mode of p11 pin 0 i/o port 1 intp10 input pmc10 specification of operation mode of p10 pin 0 i/o port 1 intp9 input (d) pull-up resistor option register 1 (pu1) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc42h 7 6 5 4 3 2 1 0 pu1 0 0 0 0 0 0 pu11 pu10 pu1n control of on-chip pull-up resistor connection (n = 0, 1) 0 not connected 1 connected chapter 4 port functions preliminary user?s manual u17717ej2v0ud 100 (e) external interrupt falling edge specification register 1 (intf1) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf1n and intr1n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc02h 7 6 5 4 3 2 1 0 intf1 0 0 0 0 0 0 intf11 intf10 remark see table 4-6 for how to specify a valid edge. (f) external interrupt rising edge specification register 1 (intr1) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf1n and intr1n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc22h 7 6 5 4 3 2 1 0 intr1 0 0 0 0 0 0 intr11 intr10 remark see table 4-6 for how to specify a valid edge. table 4-6. valid edge specification intf1n bit intr1n bit valid edge specification (n = 0, 1) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 0: control of intp9 pin n = 1: control of intp10 pin chapter 4 port functions preliminary user?s manual u17717ej2v0ud 101 4.3.5 port 3 port 3 is a 10-bit port (p30 to p39) for whic h i/o settings can be controlled in 1-bit units. (1) function of port 3 ? the input/output data of the port can be specified in 1-bit units. specified by port register 3 (p3) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 3 (pm3) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 3 (pmc3) ? control mode can be specified in 1-bit units. specified by port function control register 3 (pfc 3) and port function control expansion register 3l (pfce3l) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 3 (pu3) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 3 (intf3) and external interrupt rising edge specification register 3 (intr3) port 3 functions alternately as the following pins. table 4-7. alternate-function pins of port 3 pin name alternate-function pin name i/o remark block type p30 txda0 e-2 p31 rxda0/intp7 l-2 p32 ascka0/tip00/top00/top01 u-13 p33 tip01/top01 g-1 p34 tip10/top10 g-1 p35 tip11/top11 g-1 p36 ? c-1 p37 ? c-1 p38 txda2 e-2 port 3 p39 rxda2/intp8 i/o ? l-2 caution the p31 to p35, and p39 pins have hyster esis characteristics in the input mode of the alternate function, but do not have hyster esis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 102 (2) registers (a) port register 3 (p3) port register 3 (p3) is a 16-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the p3 register are used as the p3h register, and the lower 8 bits as the p3l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff406h, fffff407h 15 14 13 12 11 10 9 8 p3 (p3h note ) 0 0 0 0 0 0 p39 p38 7 6 5 4 3 2 1 0 (p3l) p37 p36 p35 p34 p33 p32 p31 p30 p3n control of output data (in output mode) (n = 0 to 9) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of t he p3 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the p3h register. (b) port mode register 3 (pm3) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pm3 regi ster are used as the pm3h register, and the lower 8 bits as the pm3l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffffh r/w address: fffff426h, fffff427h 15 14 13 12 11 10 9 8 pm3 (pm3h note ) 1 1 1 1 1 1 pm39 pm38 7 6 5 4 3 2 1 0 (pm3l) pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n control of i/o mode (n = 0 to 9) 0 output mode 1 input mode note to read or write bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 103 (c) port mode control register 3 (pmc3) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmc3 r egister are used as the pmc3h regi ster, and the lower 8 bits as the pmc3l register, however, these registers can be read or written in 8-bit or 1-bit units. (1/2) after reset: 0000h r/w address: fffff446h, fffff447h 15 14 13 12 11 10 9 8 pmc3 (pmc3h note 1 ) 0 0 0 0 0 0 pmc39 pmc38 7 6 5 4 3 2 1 0 (pmc3l) 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pmc39 specification of operation mode of p39 pin 0 i/o port 1 rxda2/intp8 input note 2 pmc38 specification of operation mode of p38 pin 0 i/o port 1 txda2 output pmc35 specification of operation mode of p35 pin 0 i/o port 1 tip11/top11 i/o pmc34 specification of operation mode of p34 pin 0 i/o port 1 tip10/top10 i/o notes 1. to read or write bits 8 to 15 of the pmc3 regist er in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. 2. the intp8 pin functions alternately as the rxda 2 pin. to use as the rxda2 pin, invalidate the edge detection function of t he alternate-function intp8 pin (by fixing the intf3.intf39 bit to 0 and the intr3.intr39 bit to 0). to use as the intp8 pin, stop the reception operation of uarta2 (by clearing the ua2ctl0.ua2rxe bit to 0). chapter 4 port functions preliminary user?s manual u17717ej2v0ud 104 (2/2) pmc33 specification of operation mode of p33 pin 0 i/o port 1 tip01/top01 i/o pmc32 specification of operation mode of p32 pin 0 i/o port 1 ascka0/tip00/top00/top01 i/o pmc31 specification of operation mode of p31 pin 0 i/o port 1 rxda0/intp7 input note pmc30 specification of operation mode of p30 pin 0 i/o port 1 txda0 output note the intp7 pin functions alternately as the rxda 0 pin. to use as the rxda0 pin, invalidate the edge detection function of the alternate-function intp7 pin (by fixing the intf3.intf31 and intr3.intr31 bits to 0). to use as the intp7 pin, stop the reception operation of uarta0 (by clearing the ua0ctl0.ua0rxe bit to 0). (d) port function control register 3l (pfc3l) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff466h 7 6 5 4 3 2 1 0 pfc3l 0 0 pfc35 pfc34 pfc33 pfc32 0 0 remark for how to specify a control mode, see 4.3.5 (2) (f) setting of control mode of p3 pin . chapter 4 port functions preliminary user?s manual u17717ej2v0ud 105 (e) port function control expa nsion register 3l (pfce3l) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff706h 7 6 5 4 3 2 1 0 pfce3l 0 0 0 0 0 pfce32 0 0 remark for how to specify a control mode, see 4.3.5 (2) (f) setting of control mode of p3 pin . (f) setting of control mode of p3 pin pfc35 specification of control mode of p35 pin 0 tip11 input 1 top11 output pfc34 specification of control mode of p34 pin 0 tip10 input 1 top10 output pfc33 specification of control mode of p33 pin 0 tip01 input 1 top01 output pfce32 pfc32 specification of control mode of p32 pin 0 0 ascka0 input 0 1 top01 output 1 0 tip00 input 1 1 top00 output chapter 4 port functions preliminary user?s manual u17717ej2v0ud 106 (g) pull-up resistor option register 3 (pu3) this is a 16-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 16- or 1-bit units. if the higher 8 bits of the pu3 regi ster are used as the pu3h register, and the lower 8 bits as the pu3l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc46h, fffffc47h 15 14 13 12 11 10 9 8 pu3 (pu3h note ) 0 0 0 0 0 0 pu39 pu38 7 6 5 4 3 2 1 0 (pu3l) pu37 pu36 pu35 pu34 pu33 pu32 pu31 pu30 pu3n control of on-chip pull-up resistor connection (n = 0 to 9) 0 not connected 1 connected note to read/write bits 8 to 15 of the pu3 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the pu3h register. (h) external interrupt falling edge specification register 3 (intf3) this is a 16-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 16-bit units. if the higher 8 bits of the intf3 register are used as the intf3h register, and the lower 8 bits as the intf3l register, however, these registers can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf3n and intr3n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc06h, fffffc07h 15 14 13 12 11 10 9 8 intf3 (intf3h note ) 0 0 0 0 0 0 intf39 0 7 6 5 4 3 2 1 0 (intf3l) 0 0 0 0 0 0 intf31 0 note to read/write bits 8 to 15 of the in tf3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the intf3h register. remark see table 4-8 for how to specify a valid edge. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 107 (i) external interrupt rising edge specification register 3 (intr3) this is a 16-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 16-bit units. if the higher 8 bits of the intr3 register are used as the intr3h register, and the lower 8 bits as the intr3l register, however, these registers can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf3n and intr3n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc26h, fffffc27h 15 14 13 12 11 10 9 8 intr3 (intr3h note ) 0 0 0 0 0 0 intr39 0 7 6 5 4 3 2 1 0 (intr3l) 0 0 0 0 0 0 intr31 0 note to read/write bits 8 to 15 of the intr3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the intr3h register. remark see table 4-8 for how to specify a valid edge. table 4-8. valid edge specification intf3n bit intr3n bit valid edge specification (n = 1, 9) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 1: control of intp7 pin n = 9: control of intp8 pin chapter 4 port functions preliminary user?s manual u17717ej2v0ud 108 4.3.6 port 4 port 4 is a 3-bit port (p40 to p42) for whic h i/o settings can be controlled in 1-bit units. (1) functions of port 4 ? the input/output data of the port can be specified in 1-bit units. specified by port register 4 (p4) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 4 (pm4) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 4 (pmc4) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 4 (pu4) port 4 functions alternately as the following pins. table 4-9. alternate-function pins of port 4 pin name alternate-function pin name i/o remark block type p40 sib0 e-1 p41 sob0 e-2 port 4 p42 sckb0 i/o ? e-3 caution the p40 and p42 pins have hysteresis charact eristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 109 (2) registers (a) port register 4 (p4) port register 4 (p4) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff408h 7 6 5 4 3 2 1 0 p4 0 0 0 0 0 p42 p41 p40 p4n control of output data (in output mode) (n = 0 to 2) 0 output 0. 1 output 1. (b) port mode register 4 (pm4) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff428h 7 6 5 4 3 2 1 0 pm4 1 1 1 1 1 pm42 pm41 pm40 pm4n control of input/output mode (n = 0 to 2) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 110 (c) port mode control register 4 (pmc4) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff448h 7 6 5 4 3 2 1 0 pmc4 0 0 0 0 0 pmc42 pmc41 pmc40 pmc42 specification of operation mode of p42 pin 0 i/o port 1 sckb0 i/o pmc41 specification of operation mode of p41 pin 0 i/o port 1 sob0 output pmc40 specification of operation mode of p40 pin 0 i/o port 1 sib0 input (d) pull-up resistor option register 4 (pu4) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc48h 7 6 5 4 3 2 1 0 pu4 0 0 0 0 0 pu42 pu41 pu40 pu4n control of on-chip pull-up resistor connection (n = 0 to 2) 0 not connected 1 connected chapter 4 port functions preliminary user?s manual u17717ej2v0ud 111 4.3.7 port 5 port 5 is a 6-bit port (p50 to p55) for whic h i/o settings can be controlled in 1-bit units. (1) functions of port 5 ? the input/output data of the port can be specified in 1-bit units. specified by port register 5 (p5) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 5 (pm5) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 5 (pmc5) ? control mode can be specified in 1-bit units. specified by port function control register 5 (pfc5) or port function control expansion register 5 (pfce5) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 5 (pu5) port 5 functions alternately as the following pins. table 4-10. alternate-function pins of port 5 pin name alternate-function pin name i/o remark block type p50 kr0/tiq01/toq01 u-4 p51 kr1/tiq02/toq02 u-4 p52 kr2/tiq03/toq03/ddi note u-5 p53 kr3/tiq00/toq00/ddo note u-6 p54 kr4/dck note g-2 port 5 p55 kr5/dms note i/o ? g-2 note the ddi, ddo, dck, and dms pins are for the on-ch ip debug function. to use the ddi, ddo, dck, and dms pins as port pins, not as on-chip debug pins, the following actions must be taken. <1> clear the ocdm0 bit of the ocdm register (special register) to 0. <2> fix the p05/intp2/drst pin to the lo w level until the above action has been taken. when the on-chip debug function is not used, inputting a high level to the drst pin before the above actions are taken may cause a malfunction (cpu deadlo ck). exercise utmost care in handling the p05 pin. when a high level is not input to the p05/intp2/drst pi n (when this pin is fixed to low level), it is not necessary to manipulate the ocdm.ocdm0 bit. because a pull-down resistor (30 k ? typ) is connected to the buffer of the p05/intp2/drst pin, the pin does not have to be fixed to the low level by an external source. the pull-down resistor is disconnected by clearing the ocdm0 bit to 0. caution the p50 to p55 pins have hysteresis char acteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 112 (2) registers (a) port register 5 (p5) port register 5 (p5) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff40ah 7 6 5 4 3 2 1 0 p5 0 0 p55 p54 p53 p52 p51 p50 p5n control of output data (in output mode) (n = 0 to 5) 0 output 0. 1 output 1. (b) port mode register 5 (pm5) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff42ah 7 6 5 4 3 2 1 0 pm5 1 1 pm55 pm54 pm53 pm52 pm51 pm50 pm5n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 113 (c) port mode control register 5 (pmc5) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. caution if the control mode is specified by us ing the pmc5 register wh en the pfc5.pfc5n and pfce5.pfce5n bits are the default valu es (0), the output becomes undefined. for this reason, first set the pfc5.pfc5n and pfce5.pfce5n bits, and then set the pmc5n bit to 1 to set the control mode. after reset: 00h r/w address: fffff44ah 7 6 5 4 3 2 1 0 pmc5 0 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 pmc55 specification of operation mode of p55 pin 0 i/o port 1 kr5 input pmc54 specification of operation mode of p54 pin 0 i/o port 1 kr4 input pmc53 specification of operation mode of p53 pin 0 i/o port 1 kr3/tiq00/toq00 i/o pmc52 specification of operation mode of p52 pin 0 i/o port 1 kr2/tiq03/toq03 i/o pmc51 specification of operation mode of p51 pin 0 i/o port 1 kr1/tiq02/toq02 i/o pmc50 specification of operation mode of p50 pin 0 i/o port 1 kr0/tiq01/toq01 i/o chapter 4 port functions preliminary user?s manual u17717ej2v0ud 114 (d) port function control register 5 (pfc5) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff46ah 7 6 5 4 3 2 1 0 pfc5 0 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 remark for how to specify a control mode, see 4.3.7 (2) (f) setting of control mode of p5 pin . (e) port function control ex pansion register 5 (pfce5) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff70ah 7 6 5 4 3 2 1 0 pfce5 0 0 0 0 pfce53 pfce52 pfce51 pfce50 remark for how to specify a control mode, see 4.3.7 (2) (f) setting of control mode of p5 pin . (f) setting of control mode of p5 pin caution if the control mode is specified by us ing the pmc5 register wh en the pfc5.pfc5n and pfce5.pfce5n bits are the default valu es (0), the output becomes undefined. for this reason, first set the pfc5.pfc5n and pfce5.pfce5n bits, and then set the pmc5n bit to 1 to set the control mode. pfc55 specification of control mode of p55 pin 0 setting prohibited 1 kr5 input pfc54 specification of control mode of p54 pin 0 setting prohibited 1 kr4 input chapter 4 port functions preliminary user?s manual u17717ej2v0ud 115 pfce53 pfc53 specification of control mode of p53 pin 0 0 setting prohibited 0 1 tiq00/kr3 note input 1 0 toq00 output 1 1 setting prohibited pfce52 pfc52 specification of control mode of p52 pin 0 0 setting prohibited 0 1 tiq03/kr2 note input 1 0 toq03 output 1 1 setting prohibited pfce51 pfc51 specification of control mode of p51 pin 0 0 setting prohibited 0 1 tiq02/kr1 note input 1 0 toq02 output 1 1 setting prohibited pfce50 pfc50 specification of control mode of p50 pin 0 0 setting prohibited 0 1 tiq01/kr0 note input 1 0 toq01 output 1 1 setting prohibited note the krn pin functions alternately as the tiq0m pin. to use this pin as the tiq0m pin, invalidate the key return detection function of the al ternate-function krn pin (by clearing the krm.krmn bit to 0). to use this pin as the krn pin, invalidate the edge detection function of the alternate-function tiq0m pin (n = 0 to 3, m = 0 to 3). pin name use as tiq0m pin use as krn pin kr0/tiq01 krm0 bit of krm register = 0 tq0tig2, tq0tig3 bit of tq0ioc1 register = 0 kr1/tiq02 krm1 bit of krm register = 0 tq0tig4, tq0tig5 bit of tq0ioc1 register = 0 kr2/tiq03 krm2 bit of krm register = 0 tq0tig6, tq0tig7 bit of tq0ioc1 register = 0 kr3/tiq00 krm3 bit of krm register = 0 tq0tig0, tq0tig1 bit of tq0ioc1 register = 0 tq0ees0, tq0ees1 bit of tq0ioc2 register = 0 tq0ets0, tq0ets1 bit of tq0ioc2 register = 0 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 116 (g) pull-up resistor option register 5 (pu5) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc4ah 7 6 5 4 3 2 1 0 pu5 0 0 pu55 pu54 pu53 pu52 pu51 pu50 pu5n control of on-chip pull-up resistor connection (n = 0 to 5) 0 not connected 1 connected chapter 4 port functions preliminary user?s manual u17717ej2v0ud 117 4.3.8 port 6 port 6 is a 16-bit port (p60 to p615) for which i/o settings can be controlled in 1-bit units. (1) functions of port 6 ? the input/output data of the port can be specified in 1-bit units. specified by port register 6 (p6) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 6 (pm6) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 6 (pmc6) ? control mode 1 or control mode 2 can be specified in 1-bit units. specified by port function control register 6 (pfc6) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 6 (pu6) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificati on register 6l (intf6l) and external interrupt rising edge specification register 6l (intr6l) port 6 functions alternately as the following pins. table 4-11. alternate-function pins of port 6 pin name alternate-function pin name i/o remark block type p60 intp11 n-2 p61 intp12 n-2 p62 intp13 n-2 p63 ? c-1 p64 ? c-1 p65 ? c-1 p66 ? c-1 p67 ? c-1 p68 ? c-1 p69 ? c-1 p610 tiq20/toq20 g-1 p611 tiq21/toq21 g-1 p612 tiq22/toq22 g-1 p613 tiq23/toq23 g-1 p614 ? c-1 port 6 p615 ? i/o ? c-1 caution the p60 to p62, and p610 to p613 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hyst eresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 118 (2) registers (a) port register 6 (p6) port register 6 (p6) is a 16-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the p6 register are used as the p6h register, and the lower 8 bits as the p6l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff40ch, fffff40dh 15 14 13 12 11 10 9 8 p6 (p6h note ) p615 p614 p613 p612 p611 p610 p69 p68 7 6 5 4 3 2 1 0 (p6l) p67 p66 p65 p64 p63 p62 p61 p60 p6n control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of t he p6 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the p6h register. (b) port mode register 6 (pm6) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pm6 regi ster are used as the pm6h register, and the lower 8 bits as the pm6l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff42ch, fffff42dh 15 14 13 12 11 10 9 8 pm6 (pm6h note ) pm615 pm614 pm613 pm612 pm611 pm610 pm69 pm68 7 6 5 4 3 2 1 0 (pm6l) pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 pm6n control of i/o mode (n = 0 to 15) 0 output mode 1 input mode note to read or write bits 8 to 15 of the pm6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm6h register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 119 (c) port mode control register 6 (pmc6) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmc6 r egister are used as the pmc6h regi ster, and the lower 8 bits as the pmc6l register, however, these registers can be read or written in 8-bit or 1-bit units. caution if the control mode is sp ecified by using the pmc6 regist er when the pfc6.pfc6n bit is the default value (0), the output becomes undefined (n = 0 to 8). for this reason, first set the pfc6.pfc6n bit to 1, and then set the pmc6n bit to 1 to set the control mode. (1/2) after reset: 0000h r/w address: fffff44ch, fffff44dh 15 14 13 12 11 10 9 8 pmc6 (pmc6h note ) 0 0 pmc613 pmc612 pmc611 pmc610 0 0 7 6 5 4 3 2 1 0 (pmc6l) 0 0 0 0 0 pmc62 pmc61 pmc60 pmc613 specification of operation mode of p613 pin 0 i/o port 1 tiq23/toq23 i/o pmc612 specification of operation mode of p612 pin 0 i/o port 1 tiq22/toq22 i/o pmc611 specification of operation mode of p611 pin 0 i/o port 1 tiq21/toq21 i/o pmc610 specification of operation mode of p610 pin 0 i/o port 1 tiq20/toq20 i/o note to read or write bits 8 to 15 of the pmc6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc6h register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 120 (2/2) pmc62 specification of operation mode of p62 pin 0 i/o port 1 intp13 input pmc61 specification of operation mode of p61 pin 0 i/o port 1 intp12 input pmc60 specification of operation mode of p60 pin 0 i/o port 1 intp11 input chapter 4 port functions preliminary user?s manual u17717ej2v0ud 121 (d) port function control register 6 (pfc6) this is a 16-bit register that specifies control mode 1 or 2. it can be read or written in 16-bit units. if the higher 8 bits of the pfc6 regi ster are used as the pfc6h register, and the lower 8 bits as the pfc6l register, however, these registers can be read or written in 8-bit or 1-bit units. caution if the control mode is sp ecified by using the pmc6 regist er when the pfc6.pfc6n bit is the default value (0), the output becomes undefined (n = 0 to 8). for this reason, first set the pfc6.pfc6n bit to 1, and then set the pmc6n bit to 1 to set the control mode. (1/2) after reset: 0000h r/w address: fffff46ch, fffff46dh 15 14 13 12 11 10 9 8 pfc6 (pfc6h note ) 0 0 pfc613 pfc612 pfc611 pfc610 0 0 7 6 5 4 3 2 1 0 (pfc6l) 0 0 0 0 0 pfc62 pfc61 pfc60 pfc613 specification of control mode of p613 pin 0 tiq23 input 1 toq23 output pfc612 specification of control mode of p612 pin 0 tiq22 input 1 toq22 output pfc611 specification of control mode of p611 pin 0 tiq21 input 1 toq21 output pfc610 specification of control mode of p610 pin 0 tiq20 input 1 toq20 output note to read or write bits 8 to 15 of the pfc6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc6h register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 122 (2/2) pfc62 specification of control mode of p62 pin 0 setting prohibited 1 intp13 input pfc61 specification of control mode of p61 pin 0 setting prohibited 1 intp12 input pfc60 specification of control mode of p60 pin 0 setting prohibited 1 intp11 input chapter 4 port functions preliminary user?s manual u17717ej2v0ud 123 (e) pull-up resistor option register 6 (pu6) this is a 16-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 16-bit units. if the higher 8 bits of the pu6 regi ster are used as the pu6h register, and the lower 8 bits as the pu6l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffffc4ch, fffffc4dh 15 14 13 12 11 10 9 8 pu6 (pu6h note ) pu615 pu614 pu613 pu612 pu611 pu610 pu69 pu68 7 6 5 4 3 2 1 0 (pu6l) pu67 pu66 pu65 pu64 pu63 pu62 pu61 pu60 pu6n control of on-chip pull-up resistor connection (n = 0 to 15) 0 not connected 1 connected note to read/write bits 8 to 15 of the pu6 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the pu6h register. (f) external interrupt falling edge specification register 6l (intf6l) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf6n and intr6n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc0ch 7 6 5 4 3 2 1 0 intf6l 0 0 0 0 0 intf62 intf61 intf60 remark see table 4-12 for how to specify a valid edge. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 124 (g) external interrupt rising edge specification register 6l (intr6l) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf6n and intr6n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc2ch 7 6 5 4 3 2 1 0 intr6l 0 0 0 0 0 intr62 intr61 intr60 remark see table 4-12 for how to specify a valid edge. table 4-12. valid edge specification intf6n bit intr6n bit valid edge specification (n = 0 to 2) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 0: control of intp11 pin n = 1: control of intp12 pin n = 2: control of intp13 pin chapter 4 port functions preliminary user?s manual u17717ej2v0ud 125 4.3.9 port 7 port 7 is a 16-bit port (p70 to p715) for which i/o settings can be controlled in 1-bit units. (1) functions of port 7 ? the input/output data of the port can be specified in 1-bit units. specified by port registers 7l, 7h (p7l, p7h) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode registers 7l, 7h (pm7l, pm7h) port 7 functions alternately as the following pins. table 4-13. alternate-function pins of port 7 pin name alternate-function pin name i/o remark block type p70 ani0 a-1 p71 ani1 a-1 p72 ani2 a-1 p73 ani3 a-1 p74 ani4 a-1 p75 ani5 a-1 p76 ani6 a-1 p77 ani7 a-1 p78 ani8 a-1 p79 ani9 a-1 p710 ani10 a-1 p711 ani11 a-1 p712 ani12 a-1 p713 ani13 a-1 p714 ani14 a-1 port 7 p715 ani15 i/o ? a-1 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 126 (2) registers (a) port register 7h, port register 7l (p7h, p7l) port registers 7h and 7l (p7h and p7l) are 8-bit regist ers that control reading t he pin level and writing the output level. these registers can be read or written in 8-bit or 1-bit units. they cannot be accessed in 16-bit units. after reset: undefined r/w address: fffff40fh, fffff40eh 7 6 5 4 3 2 1 0 p7h p715 p714 p713 p712 p711 p710 p79 p78 7 6 5 4 3 2 1 0 p7l p77 p76 p75 p74 p73 p72 p71 p70 p7n control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. caution do not read the p7h and p7 l registers during a/d conversion. (b) port mode registers 7h, 7l (pm7h, pm7l) these are 8-bit registers that specify an input or output mode. they c an be read or written in 8-bit or 1-bit units. these registers cannot be accessed in 16-bit units. after reset: ffh r/w address: fffff42fh, fffff42eh 7 6 5 4 3 2 1 0 pm7h pm715 pm714 pm713 pm712 pm711 pm710 pm79 pm78 7 6 5 4 3 2 1 0 pm7l pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm7n control of i/o mode (n = 0 to 15) 0 output mode 1 input mode caution to use the alternate functi on of p7n (anin), set pm7n to 1. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 127 4.3.10 port 8 port 8 is a 2-bit port (p80, p81) note for which i/o settings can be controlled in 1-bit units. note in the pd70f3709 and 70f3710, the alternat e functions of the p80 and p81 pins (rxda3 and txda3) are not available. the alternate function of the p80 pin in the pd70f3709 and 70f3710 is intp14 only. (1) functions of port 8 o the input/output data of the port can be specified in 1-bit units. specified by port register 8 (p8) o the input/output mode of the port can be specified in 1-bit units. specified by port mode register 8 (pm8) o port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 8 (pmc8) o an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 8 (pu8) o the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 8 (intf8) and external interrupt rising edge specification register 8 (intr8) port 8 functions alternately as the following pins. table 4-14. alternate-function pins of port 8 pin name alternate-function pin name i/o remark block type p80 rxda3/intp14 l-2 note 1 port 8 p81 txda3 i/o ? e-2 note 2 notes 1. block type for pd70f3709, 70f3710: l-1 2. block type for pd70f3709, 70f3710: c-1 caution the p80 pin has hysteresis characteristics in the input mode of the alternate function, but does not have hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 128 (2) registers (a) port register 8 (p8) port register 8 (p8) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff410h 7 6 5 4 3 2 1 0 p8 0 0 0 0 0 0 p81 p80 p8n control of output data (in output mode) (n = 0, 1) 0 output 0. 1 output 1. (b) port mode register 8 (pm8) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff430h 7 6 5 4 3 2 1 0 pm8 1 1 1 1 1 1 pm81 pm80 pm8n control of i/o mode (n = 0, 1) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 129 (c) port mode control register 8 (pmc8) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff450h (i) pd70f3709, 70f3710 7 6 5 4 3 2 1 0 pmc8 0 0 0 0 0 0 0 pmc80 (ii) pd70f3711, 70f3712 7 6 5 4 3 2 1 0 pmc8 0 0 0 0 0 0 pmc81 pmc80 pmc81 specification of operation mode of p81 pin 0 i/o port 1 txda3 output pmc80 specification of operation mode of p80 pin 0 i/o port 1 rxda3/intp14 input note note the pd70f3709 and 70f3710 do not have rxda3. the intp14 pin of the pd70f3711 and 70f3712 functions alternately as the rxda3 pin. to use this pin as the rxda3 pin, invalidate the edge detection function of the alternate-function intp14 pin (by clearing the intf8.intf80 bit to 0 and the intr8.intr80 bit to 0). to use this pin as the intp14 pin, stop the recept ion operation of uarta3 (by clearing the ua3ctl0.ua3rxe bit to 0). (d) pull-up resistor option register 8 (pu8) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc50h 7 6 5 4 3 2 1 0 pu8 0 0 0 0 0 0 pu81 pu80 pu8n control of on-chip pull-up resistor connection (n = 0, 1) 0 not connected 1 connected chapter 4 port functions preliminary user?s manual u17717ej2v0ud 130 (e) external interrupt falling edge specification register 8 (intf8) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf80 and intr80 bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address fffffc10h 7 6 5 4 3 2 1 0 intf8 0 0 0 0 0 0 0 intf80 remark see table 4-15 for how to specify a valid edge. (f) external interrupt rising edge specification register 8 (intr8) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf80 and intr80 bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address fffffc30h 7 6 5 4 3 2 1 0 intr8 0 0 0 0 0 0 0 intr80 remark see table 4-15 for how to specify a valid edge. table 4-15. valid edge specification intf80 bit intr80 bit valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark control of intp14 pin chapter 4 port functions preliminary user?s manual u17717ej2v0ud 131 4.3.11 port 9 port 9 is a 9-bit or 16-bit port (p90 to p915) fo r which i/o settings can be controlled in 1-bit units. (1) functions of port 9 ? the input/output data of the port can be specified in 1-bit units. specified by port register 9 (p9) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 9 (pm9) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 9 (pmc9) ? control mode can be specified in 1-bit units. specified by port function control register 9 (pfc9) and port function control expansion register 9 (pfce9) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 9 (pu9) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificati on register 9h (intf9h) and external interrupt rising edge specification regi ster 9h (intr9h) port 9 functions alternately as the following pins. table 4-16. alternate-function pins of port 9 pin name alternate-function pin name i/o remark block type p90 kr6/txda1 u-12 p91 kr7/rxda1 u-7 p92 tiq11/toq11 u-11 p93 tiq12/toq12 u-11 p94 tiq13/toq13 u-11 p95 tiq10/toq10 u-11 p96 tip21/top21 u-9 p97 sib1/tip20/top20 u-8 p98 sob1 g-3 p99 sckb1 g-5 p910 sib2 g-4 p911 sob2 g-3 p912 sckb2 g-5 p913 intp4/pcl w-1 p914 intp5 n-2 port 9 p915 intp6 i/o ? n-2 caution the p90 to p97, p99, p910, and p912 to p 915 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 132 (2) registers (a) port register 9 (p9) port register 9 (p9) is a 16-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the p9 register are used as the p9h register, and the lower 8 bits as the p9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff412h, fffff413h 15 14 13 12 11 10 9 8 p9 (p9h note ) p915 p914 p913 p912 p911 p910 p99 p98 7 6 5 4 3 2 1 0 (p9l) p97 p96 p95 p94 p93 p92 p91 p90 p9n control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of t he p9 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the p9h register. (b) port mode register 9 (pm9) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pm9 regi ster are used as the pm9h register, and the lower 8 bits as the pm9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffffh r/w address: fffff432h, fffff433h 15 14 13 12 11 10 9 8 pm9 (pm9h note ) pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 7 6 5 4 3 2 1 0 (pm9l) pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n control of i/o mode (n = 0 to 15) 0 output mode 1 input mode note to read or write bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 133 (c) port mode control register 9 (pmc9) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmc9 r egister are used as the pmc9h regi ster, and the lower 8 bits as the pmc9l register, however, these registers can be read or written in 8-bit or 1-bit units. caution if the control mode is specified by us ing the pmc9 register wh en the pfc9.pfc9n bit and the pfce9.pfce9n bit are the default values (0), the output becomes undefined. for this reason, first set the pfc9.pfc9n bi t and the pfce9. pfce9n bit to 1, and then set the pmc9n bit to 1 to set the control mode. (1/3) after reset: 0000h r/w address: fffff452h, fffff453h 15 14 13 12 11 10 9 8 pmc9 (pmc9h note ) pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 7 6 5 4 3 2 1 0 (pmc9l) pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 specification of operation mode of p915 pin 0 i/o port 1 intp6 input pmc914 specification of operation mode of p914 pin 0 i/o port 1 intp5 input pmc913 specification of operation mode of p913 pin 0 i/o port 1 intp4/pcl i/o pmc912 specification of operation mode of p912 pin 0 i/o port 1 sckb2 i/o note to read or write bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 134 (2/3) pmc911 specification of operation mode of p911 pin 0 i/o port 1 sob2 output pmc910 specification of operation mode of p910 pin 0 i/o port 1 sib2 input pmc99 specification of operation mode of p99 pin 0 i/o port 1 sckb1 i/o pmc98 specification of operation mode of p98 pin 0 i/o port 1 sob1 output pmc97 specification of operation mode of p97 pin 0 i/o port 1 sib1/tip20/top20 i/o pmc96 specification of operation mode of p96 pin 0 i/o port 1 tip21/top21 i/o pmc95 specification of operation mode of p95 pin 0 i/o port 1 tiq10/toq10 i/o pmc94 specification of operation mode of p94 pin 0 i/o port 1 tiq13/toq13 i/o pmc93 specification of operation mode of p93 pin 0 i/o port 1 tiq12/toq12 i/o chapter 4 port functions preliminary user?s manual u17717ej2v0ud 135 (3/3) pmc92 specification of operation mode of p92 pin 0 i/o port 1 tiq11/toq11 i/o pmc91 specification of operation mode of p91 pin 0 i/o port 1 kr7/rxda1 input pmc90 specification of operation mode of p90 pin 0 i/o port 1 kr6/txda1 i/o (d) port function control register 9 (pfc9) this is a 16-bit register that specif ies control mode 1, 2, 3, or 4. it can be read or written in 16-bit units. if the higher 8 bits of the pfc9 regi ster are used as the pfc9h register, and the lower 8 bits as the pfc9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffff472h, fffff473h 15 14 13 12 11 10 9 8 pfc9 (pfc9h note ) pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 7 6 5 4 3 2 1 0 (pfc9l) pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 note to read or write bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. remark for how to specify a control mode, see 4.3.11 (2) (f) setting of control mode of p9 pin . chapter 4 port functions preliminary user?s manual u17717ej2v0ud 136 (e) port function control ex pansion register 9 (pfce9) this is a 16-bit register that specif ies control mode 1, 2, 3, or 4. it can be read or written in 16-bit units. if the higher 8 bits of the pfc9 regi ster are used as the pfc9h register, and the lower 8 bits as the pfc9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffff712h, fffff713h 15 14 13 12 11 10 9 8 pfce9 (pfce9h note ) 0 0 pfce913 0 0 0 0 0 7 6 5 4 3 2 1 0 (pfce9l) pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 note to read or write bits 8 to 15 of the pfce9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfce9h register. remark for how to specify a control mode, see 4.3.11 (2) (f) setting of control mode of p9 pin . chapter 4 port functions preliminary user?s manual u17717ej2v0ud 137 (f) setting of control mode of p9 pin caution if the control mode is specified by us ing the pfc9 register wh en the pfc9.pfc9n and pfce9.pfce9n bits are the default valu es (0), the output becomes undefined. for this reason, first set the pfc9.pfc9n and pfce9.pfce9n bits, and then set the pmc9n bit to 1 to set the control mode. pfc915 specification of control mode of p915 pin 0 setting prohibited 1 intp6 input pfc914 specification of control mode of p914 pin 0 setting prohibited 1 intp5 input pfce913 pfc913 specification of control mode of p913 pin 0 0 setting prohibited 0 1 intp4 input 1 0 pcl output 1 1 setting prohibited pfc912 specification of control mode of p912 pin 0 setting prohibited 1 sckb2 i/o pfc911 specification of control mode of p911 pin 0 setting prohibited 1 sob2 output pfc910 specification of control mode of p910 pin 0 setting prohibited 1 sib2 input pfc99 specification of control mode of p99 pin 0 setting prohibited 1 sckb1 i/o pfc98 specification of control mode of p98 pin 0 setting prohibited 1 sob1 input chapter 4 port functions preliminary user?s manual u17717ej2v0ud 138 pfce97 pfc97 specification of control mode of p97 pin 0 0 setting prohibited 0 1 sib1 input 1 0 tip20 input 1 1 top20 output pfce96 pfc96 specification of control mode of p96 pin 0 0 setting prohibited 0 1 setting prohibited 1 0 tip21 input 1 1 top21 output pfce95 pfc95 specification of control mode of p95 pin 0 0 setting prohibited 0 1 tiq10 input 1 0 toq10 output 1 1 setting prohibited pfce94 pfc94 specification of control mode of p94 pin 0 0 setting prohibited 0 1 tiq13 input 1 0 toq13 output 1 1 setting prohibited pfce93 pfc93 specification of control mode of p93 pin 0 0 setting prohibited 0 1 tiq12 input 1 0 toq12 output 1 1 setting prohibited pfce92 pfc92 specification of control mode of p92 pin 0 0 setting prohibited 0 1 tiq11 input 1 0 toq11 output 1 1 setting prohibited chapter 4 port functions preliminary user?s manual u17717ej2v0ud 139 pfce91 pfc91 specification of control mode of p91 pin 0 0 setting prohibited 0 1 kr7 input 1 0 kr7/rxda1 input note 1 1 setting prohibited pfce90 pfc90 specification of control mode of p90 pin 0 0 setting prohibited 0 1 kr6 input 1 0 txda1 output 1 1 setting prohibited note the kr7 pin and rxda1 pin are alternate-function pins. when using the pin as the rxda1 pin, disable kr7 pin key return detection. (clear the krm7 bit of the krm register to 0.) also, when usin g the pin as the kr7 pin, it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 140 (g) pull-up resistor option register 9 (pu9) this is a 16-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 16-bit units. if the higher 8 bits of the pu9 regi ster are used as the pu9h register, and the lower 8 bits as the pu9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffffc52h, fffffc53h 15 14 13 12 11 10 9 8 pu9 (pu9h note ) pu915 pu914 pu913 pu912 pu911 pu910 pu99 pu98 7 6 5 4 3 2 1 0 (pu9l) pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 pu9n control of on-chip pull-up resistor connection (n = 0 to 15) 0 not connected 1 connected note to read/write bits 8 to 15 of the pu9 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the pu9h register. (h) external interrupt falling edge specification register 9h (intf9h) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf9n and intr9n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc13h 7 6 5 4 3 2 1 0 intf9h intf915 intf914 intf913 0 0 0 0 0 remark see table 4-17 for how to specify a valid edge. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 141 (i) external interrupt rising edge specification register 9h (intr9h) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf9n and intr9n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc33h 7 6 5 4 3 2 1 0 intr9h intr915 intr914 intr913 0 0 0 0 0 remark see table 4-17 for how to specify a valid edge. table 4-17. valid edge specification intf9n bit intr9n bit valid edge specification (n = 13 to 15) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13: control of intp4 pin n = 14: control of intp5 pin n = 15: control of intp6 pin chapter 4 port functions preliminary user?s manual u17717ej2v0ud 142 4.3.12 port 12 port 12 is an 8-bit port (p120 to p127) for which i/o settings can be controlled in 1-bit units. (1) functions of port 12 ? the input/output data of the port can be specified in 1-bit units. specified by port register 12 (p12) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 12 (pm12) port 12 functions alternately as the following pins. table 4-18. alternate-function pins of port 12 pin name alternate-function pin name i/o remark block type p120 ani16 a-1 p121 ani17 a-1 p122 ani18 a-1 p123 ani19 a-1 p124 ani20 a-1 p125 ani21 a-1 p126 ani22 a-1 port 12 p127 ani23 i/o ? a-1 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 143 (2) registers (a) port register 12 (p12) port register 12 (p12) is an 8-bit r egister that controls reading the pi n level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff418h 7 6 5 4 3 2 1 0 p12 p127 p126 p125 p124 p123 p122 p121 p120 p12n control of output data (in output mode) (n = 0 to 7) 0 output 0. 1 output 1. (b) port mode register 12 (pm12) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff438h 7 6 5 4 3 2 1 0 pm12 pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 pm12n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode caution to use the alternate function of p12n (anin), set pm12n to 1. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 144 4.3.13 port cd port cd is a 4-bit port (pcd0 to pcd3) for wh ich i/o settings can be cont rolled in 1-bit units. (1) functions of port cd ? the input/output data of the port can be specified in 1-bit units. specified by port register cd (pcd) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register cd (pmcd) port cd functions alternately as the following pins. table 4-19. alternate-function pins of port cd pin name alternate-function pin name i/o remark block type pcd0 ? b-1 pcd1 ? b-1 pcd2 ? b-1 port cd pcd3 ? i/o ? b-1 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 145 (2) registers (a) port register cd (pcd) port register cd (pcd) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff00eh 7 6 5 4 3 2 1 0 pcd 0 0 0 0 pcd3 pcd2 pcd1 pcd0 pcdn control of output data (in output mode) (n = 0 to 3) 0 output 0. 1 output 1. (b) port mode register cd (pmcd) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff02eh 7 6 5 4 3 2 1 0 pmcd 1 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0 pmcdn control of i/o mode (n = 0 to 3) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 146 4.3.14 port cm port cm is a 6-bit port (pcm0 to pcm5) for wh ich i/o settings can be cont rolled in 1-bit units. (1) functions of port cm ? the input/output data of the port can be specified in 1-bit units. specified by port register cm (pcm) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register cm (pmcm) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register cm (pmccm) port cm functions alternately as the following pins. table 4-20. alternate-function pins of port cm pin name alternate-function pin name i/o remark block type pcm0 wait d-1 pcm1 clkout d-2 pcm2 hldak d-2 pcm3 cldrq d-1 pcm4 ? b-1 port cm pcm5 ? i/o ? b-1 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 147 (2) registers (a) port register cm (pcm) port register cm (pcm) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff00ch 7 6 5 4 3 2 1 0 pcm 0 0 pcm5 pcm4 pcm3 pcm2 pcm1 pcm0 pcmn control of output data (in output mode) (n = 0 to 5) 0 output 0. 1 output 1. (b) port mode register cm (pmcm) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff02ch 7 6 5 4 3 2 1 0 pmcm 1 1 pmcm5 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0 pmcmn control of i/o mode (n = 0 to 5) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 148 (c) port mode control register cm (pmccm) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff04ch 7 6 5 4 3 2 1 0 pmccm 0 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 pmccm3 specification of operation mode of pcm3 pin 0 i/o port 1 hldrq input pmccm2 specification of operation mode of pcm2 pin 0 i/o port 1 hldak output pmccm1 specification of operation mode of pcm1 pin 0 i/o port 1 clkout output pmccm0 specification of operation mode of pcm0 pin 0 i/o port 1 wait input chapter 4 port functions preliminary user?s manual u17717ej2v0ud 149 4.3.15 port cs port cs is an 8-bit port (pcs0 to pcs7) for wh ich i/o settings can be cont rolled in 1-bit units. (1) functions of port cs ? the input/output data of the port can be specified in 1-bit units. specified by port register cs (pcs) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register cs (pmcs) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register cs (pmccs) port cs functions alternately as the following pins. table 4-21. alternate-function pins of port cs pin name alternate-function pin name i/o remark block type pcs0 cs0 d-2 pcs1 cs1 d-2 pcs2 cs2 d-2 pcs3 cs3 d-2 pcs4 ? b-1 pcs5 ? b-1 pcs6 ? b-1 port cs pcs7 ? i/o ? b-1 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 150 (2) registers (a) port register cs (pcs) port register cs (pcs) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff008h 7 6 5 4 3 2 1 0 pcs pcs7 pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 pcsn control of output data (in output mode) (n = 0 to 7) 0 output 0. 1 output 1. (b) port mode register cs (pmcs) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff028h 7 6 5 4 3 2 1 0 pmcs pmcs7 pmcs6 pmcs5 pmcs4 pmcs3 pmcs2 pmcs1 pmcs0 pmcsn control of i/o mode (n = 0 to 7) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 151 (c) port mode control register cs (pmccs) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff048h 7 6 5 4 3 2 1 0 pmccs 0 0 0 0 pmccs3 pmccs2 pmccs1 pmccs0 pmccs3 specification of operation mode of pcs3 pin 0 i/o port 1 cs3 output pmccs2 specification of operation mode of pcs2 pin 0 i/o port 1 cs2 output pmccs1 specification of operation mode of pcs1 pin 0 i/o port 1 cs1 output pmccs0 specification of operation mode of pcs0 pin 0 i/o port 1 cs0 output chapter 4 port functions preliminary user?s manual u17717ej2v0ud 152 4.3.16 port ct port ct is an 8-bit port (pct0 to pct7) for wh ich i/o settings can be cont rolled in 1-bit units. (1) functions of port ct ? the input/output data of the port can be specified in 1-bit units. specified by port register ct (pct) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register ct (pmct) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register ct (pmcct) port ct functions alternately as the following pins. table 4-22. alternate-function pins of port ct pin name alternate-function pin name i/o remark block type pct0 wr0 d-2 pct1 wr1 d-2 pct2 ? b-1 pct3 ? b-1 pct4 rd d-2 pct5 ? b-1 pct6 astb d-2 port ct pct7 ? i/o ? b-1 chapter 4 port functions preliminary user?s manual u17717ej2v0ud 153 (2) registers (a) port register ct (pct) port register ct (pct) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff00ah 7 6 5 4 3 2 1 0 pct pct7 pct6 pct5 pct4 pct3 pct2 pct1 pct0 pctn control of output data (in output mode) (n = 0 to 7) 0 output 0. 1 output 1. (b) port mode register ct (pmct) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff02ah 7 6 5 4 3 2 1 0 pmct pmct7 pmct6 pmct5 pmct 4 pmct3 pmct2 pmct1 pmct0 pmctn control of i/o mode (n = 0 to 7) 0 output mode 1 input mode chapter 4 port functions preliminary user?s manual u17717ej2v0ud 154 (c) port mode control register ct (pmcct) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff04ah 7 6 5 4 3 2 1 0 pmcct 0 pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 pmcct6 specification of operation mode of pct3 pin 0 i/o port 1 astb output pmcct4 specification of operation mode of pct2 pin 0 i/o port 1 rd output pmcct1 specification of operation mode of pct1 pin 0 i/o port 1 wr1 output pmcct0 specification of operation mode of pct0 pin 0 i/o port 1 wr0 output chapter 4 port functions preliminary user?s manual u17717ej2v0ud 155 4.3.17 port dl port dl is a 16-bit port (pdl0 to pdl15) for wh ich i/o settings can be controlled in 1-bit units. (1) function of port dl ? the input/output data of the port can be specified in 1-bit units. specified by port register dl (pdl) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register dl (pmdl) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register dl (pmcdl) port dl functions alternately as the following pins. table 4-23. alternate-function pins of port dl pin name alternate-function pin name i/o remark pdl0 ad0 d-3 pdl1 ad1 d-3 pdl2 ad2 d-3 pdl3 ad3 d-3 pdl4 ad4 d-3 pdl5 ad5/flmd1 note d-3 pdl6 ad6 d-3 pdl7 ad7 d-3 pdl8 ad8 d-3 pdl9 ad9 d-3 pdl10 ad10 d-3 pdl11 ad11 d-3 pdl12 ad12 d-3 pdl13 ad13 d-3 pdl14 ad14 d-3 port dl pdl15 ad15 i/o ? d-3 note because the flmd1 pin is used in the flash progra mming mode, it does not have to be manipulated by using a port control register. for details, see chapter 24 flash memory . chapter 4 port functions preliminary user?s manual u17717ej2v0ud 156 (2) registers (a) port register dl (pdl) port register dl (pdl) is a 16-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the pdl regi ster are used as the pdlh register , and the lower 8 bits as the pdll register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff004h, fffff005h 15 14 13 12 11 10 9 8 pdl (pdlh note ) pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 7 6 5 4 3 2 1 0 (pdll) pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdln control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pdlh register. (b) port mode register dl (pmdl) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmdl register are used as the pmdlh register, and the lower 8 bits as the pmdll register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffffh r/w address: fffff024h, fffff025h 15 14 13 12 11 10 9 8 pmdl (pmdlh note ) pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 7 6 5 4 3 2 1 0 (pmdll) pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 pmdln control of i/o mode (n = 0 to 15) 0 output mode 1 input mode note to read or write bits 8 to 15 of t he pmdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmdlh register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 157 (c) port mode control register dl (pmcdl) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmcdl register are used as the pmcdlh register, and the lower 8 bits as the pmcdll register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffff044h, fffff045h 15 14 13 12 11 10 9 8 pmcdl (pmcdlh note ) pmcdl15 pmcdl14 pmcdl13 pmcdl12 pmcdl11 pmcdl10 pmcdl9 pmcdl8 7 6 5 4 3 2 1 0 (pmcdll) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 pmcdln specification of operation mode of pdl15 pin (n = 0 to 15) 0 i/o port 1 adn i/o (address/data bus i/o) note to read or write bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmcdlh register. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 158 4.3.18 port pins that function alternately as on-chip debug function the pins shown in table 4-24 function alternately as on -chip debug pins. after an external reset, these pins are initialized as on-chip debug pins (drst, ddi, ddo, dck, and dms). table 4-24. on-chip debug pins pin name alternate function pin p05 intp2/drst p52 kr2/tiq03/toq03/ddi p53 kr3/tiq00/toq00/ddo p54 kr4/dck p55 kr5/dms to use these pins as port pins, not as on-chip debug pi ns, the following actions must be taken after an external reset. <1> clear the ocdm0 bit of the ocdm register (special register) to 0. <2> fix the p05/intp2/drst pin to the low le vel until the above action has been taken. when the on-chip debug function is not used, inputting a high level to the drst pin before the above actions are taken may cause a malfunction (cpu deadlock). exercise utmost care in handling the p05 pin. when a high level is not input to the p05/intp2/drst pin (when th is pin is fixed to low level), it is not necessary to manipulate the ocdm.ocdm0 bit. because a pull-down resistor (30 k ? typ) is connected to the buffer of the p05/intp2/drst pin, the pin does not have to be fixed to the low level by an external source. the pull-down resistor is disc onnected by clearing the ocdm0 bit to 0. for details, see chapter 26 on-chip debug function . chapter 4 port functions preliminary user?s manual u17717ej2v0ud 159 4.3.19 register settings to use port pins as alternate-function pins table 4-25. register settings to use po rt pins as alternate-function pins (1/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) tip31 input setting not required pmc00 = 1 pfc00 = 0 ? p00 top31 output setting not required pmc00 = 1 pfc00 = 1 ? tip30 input setting not required pmc01 = 1 pfc01 = 0 ? p01 top30 output setting not required pmc01 = 1 pfc01 = 1 ? p02 nmi input setting not required pmc02 = 1 ? ? intp0 input setting not required pmc03 = 1 pfc03 = 0 ? intx03 (intx0) p03 adtrg output setting not required pmc03 = 1 pfc03 = 1 ? p04 intp1 input setting not required pmc04 = 1 ? ? intx04 (intx0) intp2 input setting not required pmc05 = 1 ? ? intx05 (intx0) p05 note drst input setting not required setting not required ? ? ocdm0 (ocdm) = 1 p06 intp3 input setting not required pmc06 = 1 ? ? intx06 (intx0) p10 intp9 input setting not required pmc10 = 1 ? ? intx10 (intx1) p11 intp10 input setting not required pmc11 = 1 ? ? intx11 (intx1) note after an external reset, the p05/intp2/drst pin is initia lized as an on-chip debug pin (drst). to not use the p05/intp2/drst pin as an on-chip debug pin, see chapter 26 on-chip debug function . remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions preliminary user?s manual u17717ej2v0ud 160 table 4-25. register settings to use po rt pins as alternate-function pins (2/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) p30 txda0 output setting not required pmc30 = 1 ? ? rxda0 input setting not required pmc31 = 1 ? ? note 1 p31 intp7 input setting not required pmc31 = 1 ? ? note 1 , intx31 (intx3) ascka0 input setting not required pmc32 = 1 pfc32 = 0 pfce32 = 0 top01 output setting not required pmc32 = 1 pfc32 = 1 pfce32 = 0 tip00 input setting not required pmc32 = 1 pfc32 = 0 pfce32 = 1 p32 top00 output setting not required pmc32 = 1 pfc32 = 1 pfce32 = 1 tip01 input setting not required pmc33 = 1 pfc33 = 0 ? p33 top01 output setting not required pmc33 = 1 pfc33 = 1 ? tip10 input setting not required pmc34 = 1 pfc34 = 0 ? p34 top10 output setting not required pmc34 = 1 pfc34 = 1 ? tip11 input setting not required pmc35 = 1 pfc35 = 0 ? p35 top11 output setting not required pmc35 = 1 pfc35 = 1 ? p38 txda2 output setting not required pmc38 = 1 ? ? rxda2 input setting not required pmc39 = 1 ? ? note 2 p39 intp8 input setting not required pmc39 = 1 ? ? note 2 , intx39 (intx3) p40 sib0 input setting not required pmc40 = 1 ? ? p41 sob0 output setting not required pmc41 = 1 ? ? p42 sckb0 i/o setting not required pmc42 = 1 ? ? notes 1. the intp7 pin functions alternately as the rxda0 pin. to use this pin as the rxda0 pin, invalidate the edge detection function of the alternate-function intp7 pin (by clearing the intf31 bit of the intf3 register to 0 and the intr31 bit of the intr3 register to 0). to use this pin as the in tp7 pin, stop the reception operation of uarta0 (by clearing the ua0rxe bit of the ua0ctl0 register to 0). 2. the intp8 pin functions alternately as the rxda2 pin. to use this pin as the rxda2 pin, invalidate the edge detection function of the alternate-function intp8 pin (by clearing the intf39 bit of the intf3 register to 0 and the intr39 bit of the intr3 register to 0). to use this pin as the in tp8 pin, stop the reception operation of uarta2 (by clearing the ua2rxe bit of the ua2ctl0 register to 0). remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions preliminary user?s manual u17717ej2v0ud 161 table 4-25. register settings to use po rt pins as alternate-function pins (3/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) kr0 input setting not required pmc50 = 1 pfc50 = 1 pfce50 = 0 note 1 tiq01 input setting not required pmc50 = 1 pfc50 = 1 pfce50 = 0 note 1 p50 toq01 output setting not required pmc50 = 1 pfc50 = 0 pfce50 = 1 kr1 input setting not required pmc51 = 1 pfc51 = 1 pfce54 = 0 note 1 tiq02 input setting not required pmc51 = 1 pfc51 = 1 pfce51 = 0 note 1 p51 toq02 output setting not required pmc51 = 1 pfc51 = 0 pfce51 = 1 kr2 input setting not required pmc52 = 1 pfc52 = 1 pfce52 = 0 note 1 tiq03 input setting not required pmc52 = 1 pfc52 = 1 pfce52 = 0 note 1 toq03 output setting not required pmc52 = 1 pfc52 = 0 pfce52 = 1 p52 ddi note 2 input setting not required setting not required setting not required setting not required ocdm0 (ocdm) = 1 kr3 input setting not required pmc53 = 1 pfc53 = 1 pfce53 = 0 note 1 tiq00 input setting not required pmc53 = 1 pfc53 = 1 pfce53 = 0 note 1 toq00 output setting not required pmc53 = 1 pfc53 = 0 pfce53 = 1 p53 ddo note 2 output setting not required setting not required setting not required setting not required ocdm0 (ocdm) = 1 kr4 input setting not required pmc54 = 1 pfc54 = 1 ? p54 dck note 2 output setting not required setting not required setting not required ? ocdm0 (ocdm) = 1 kr5 input setting not required pmc55 = 1 pfc55 = 1 ? p55 dms note 2 output setting not required setting not required setting not required ? ocdm0 (ocdm) = 1 notes 1. the kr7 pin functions alternately as the tiq0m pin. to use this pin as the tiq0m pin, invalidate the key return detection function of the alternate-function krn pin (by clearing the krmn bit of the krm register to 0). to use this pin as the krn pin, invalidate the ed ge detection function of the alternate-function tiq0m pin (n = 0 to 3, m = 0 to 3). pin name when used as tiq0m pin when used as krn pin kr0/tiq01 krm0 bit of krm register = 0 tq0t ig2, tq0tig3 bits of tq0ioc1 register = 0 kr1/tiq02 krm1 bit of krm register = 0 tq0t ig4, tq0tig5 bits of tq0ioc1 register = 0 kr2/tiq03 krm2 bit of krm register = 0 tq0t ig6, tq0tig7 bits of tq0ioc1 register = 0 kr3/tiq00 krm3 bit of krm register = 0 tq0tig0, tq0tig1 bits of tq0ioc1 register = 0 tq0ees0, tq0ees1 bits of tq0ioc2 register = 0 tq0ets0, tq0ets1 bits of tq0ioc2 register = 0 2. the ddi, ddo, dck, and dms pins are on-chip debug pins . to not use these pins as on-chip debug pins after an external reset, see chapter 26 on-chip debug function . caution if the control mode is sp ecified by using the pmc5 register when the pfc5.pfc5n bit and the pfce5.pfce5n bit are the default valu es (0), the output becomes undefined. for this reason, first set the pfc5.pfc5n bit and the pfce5.pfce5n bit, an d then set the pmc5n bit to 1 to set the control mode. remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions preliminary user?s manual u17717ej2v0ud 162 table 4-25. register settings to use po rt pins as alternate-function pins (4/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) p60 intp11 input setting not required pmc60 = 1 pfc60 = 1 ? intx60 (intx6l) p61 intp12 input setting not required pmc61 = 1 pfc61 = 1 ? intx61 (intx6l) p62 intp13 input setting not required pmc62 = 1 pfc62 = 1 ? intx62 (intx6l) tiq20 input setting not required pmc610 = 1 pfc610 = 0 ? p610 toq20 output setting not required pmc610 = 1 pfc610 = 1 ? tiq21 input setting not required pmc611 = 1 pfc611 = 0 ? p611 toq21 output setting not required pmc611 = 1 pfc611 = 1 ? tiq22 input setting not required pmc612 = 1 pfc612 = 0 ? p612 toq22 output setting not required pmc612 = 1 pfc612 = 1 ? tiq23 input setting not required pmc613 = 1 pfc613 = 0 ? p613 toq23 output setting not required pmc613 = 1 pfc613 = 1 ? p70 ani0 input pm70 = 1 note ? ? ? p71 ani1 input pm71 = 1 note ? ? ? p72 ani2 input pm72 = 1 note ? ? ? p73 ani3 input pm73 = 1 note ? ? ? p74 ani4 input pm74 = 1 note ? ? ? p75 ani5 input pm75 = 1 note ? ? ? p76 ani6 input pm76 = 1 note ? ? ? p77 ani7 input pm77 = 1 note ? ? ? p78 ani8 input pm78 = 1 note ? ? ?? p79 ani9 input pm79 = 1 note ? ? ? p710 ani10 input pm710 = 1 note ? ? ? p711 ani11 input pm711 = 1 note ? ? ? p712 ani12 input pm712 = 1 note ? ? ? p713 ani13 input pm713 = 1 note ? ? ? p714 ani14 input pm714 = 1 note ? ? ? p715 ani15 input pm715 = 1 note ? ? ? note set pm7n to 1 to use the alternate function of p7n (anin). caution if the control mode is specified by using the pm c6 register when the pfc6.p fc6n bit (n = 0 to 8) is the default value (0), the output becomes undefined. for this reason, first set the pfc6.pfc6n bit and th en set the pmc6n bit to 1 to set the control mode. remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions preliminary user?s manual u17717ej2v0ud 163 table 4-25. register settings to use port pin as alternate-function pins (5/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) rxda3 input setting not required pmc80 = 1 ? ? note 2 p80 intp14 input setting not required pmc80 = 1 ? ? note 2, intx80 (intx8) p81 txda3 output setting not required pmc81 = 1 ? ? kr6 input setting not required pmc90 = 1 pfc90 = 1 pfce90 = 0 p90 txda1 output setting not required pmc90 = 1 pfc90 = 0 pfce90 = 1 pfc91 = 1 pfce91 = 0 kr7 note 1 input setting not required pmc91 = 1 pfc91 = 0 pfce91 = 1 p91 rxda1 input setting not required pmc91 = 1 pfc91 = 0 pfce91 = 1 tiq11 input setting not required pmc92 = 1 pfc92 = 1 pfce92 = 0 p92 toq11 output setting not required pmc92 = 1 pfc92 = 0 pfce92 = 1 tiq12 input setting not required pmc93 = 1 pfc93 = 1 pfce93 = 0 p93 toq12 output setting not required pmc93 = 1 pfc93 = 0 pfce93 = 1 tiq13 input setting not required pmc94 = 1 pfc94 = 1 pfce94 = 0 p94 toq13 output setting not required pmc94 = 1 pfc94 = 0 pfce94 = 1 tiq10 input setting not required pmc95 = 1 pfc95 = 1 pfce95 = 0 p95 toq10 output setting not required pmc95 = 1 pfc95 = 0 pfce95 = 1 tip21 input setting not required pmc96 = 1 pfc96 = 0 pfce96 = 1 p96 top21 output setting not required pmc96 = 1 pfc96 = 1 pfce96 = 1 sib1 input setting not required pmc97 = 1 pfc97 = 1 pfce97 = 0 tip20 input setting not required pmc97 = 1 pfc97 = 0 pfce97 = 1 p97 top20 output setting not required pmc97 = 1 pfc97 = 1 pfce97 = 1 p98 sob1 output setting not required pmc98 = 1 pfc98 = 1 ? p99 sckb1 i/o setting not required pmc99 = 1 pfc99 = 1 ? p910 sib2 input setting not required pmc910 = 1 pfc910 = 1 ? p911 sob2 output setting not required pmc911 = 1 pfc911 = 1 ? p912 sckb2 i/o setting not required pmc912 = 1 pfc912 = 1 ? intp4 input setting not required pmc913 = 1 pfc913 = 1 pfce913 = 0 intx913 (intx9h) p913 pcl output setting not required pmc913 = 1 pfc913 = 0 pfce913 = 1 p914 intp5 input setting not required pmc914 = 1 pfc914 = 1 ? intx914 (intx9h) p915 intp6 input setting not required pmc915 = 1 pfc915 = 1 ? intx915 (intx9h) notes 1. the kr7 pin and rxda1 pin are alternate-function pins. when using the pin as the rxda1 pin, disable kr7 pin key return detection. (clear the krm.krm7 bit to 0.) also, when using the pin as the kr7 pin, it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0. 2. the intp14 pin functions alternately as the rxda3 pin. to use this pi n as the rxda3 pin, invalidate the edge detection function of the alte rnate-function intp14 pin (by clearing the intf8.intf80 bit to 0 and the intr8.intr80 bit to 0). to use this pin as the in tp14 pin, stop the reception operation of uarta3 (by clearing the ua3ctl0.ua3rxe bit to 0). caution if the control mode is specified by using the pmc9 register when th e pfc9.pfc9n bit and the pfce9.pfce9n bit are the default valu es (0), the output becomes undefined. for this reason, first set the pfc9.pfc9n bit and the pfce9.pfce9n bit, an d then set the pmc9n bit to 1 to set the control mode. remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions preliminary user?s manual u17717ej2v0ud 164 table 4-25. register settings to use po rt pins as alternate-function pins (6/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) p120 ani16 input pm120 = 1 note ? ? ? p121 ani17 input pm121 = 1 note ? ? ? p122 ani18 input pm122 = 1 note ? ? ? p123 ani19 input pm123 = 1 note ? ? ? p124 ani20 input pm124 = 1 note ? ? ? p125 ani21 input pm125 = 1 note ? ? ? p126 ani22 input pm126 = 1 note ? ? ? p127 ani23 input pm127 = 1 note ? ? ? pcm0 wait input setting not required pmccm0 = 1 ? ? pcm1 clkout output setting not required pmccm1 = 1 ? ? pcm2 hldak output setting not required pmccm2 = 1 ? ? pcm3 hldrq input setting not required pmccm3 = 1 ? ? pcs0 cs0 output setting not required pmccs0 = 1 ? ? pcs1 cs1 output setting not required pmccs1 = 1 ? ? pcs2 cs2 output setting not required pmccs2 = 1 ? ? pcs3 cs3 output setting not required pmccs3 = 1 ? ? pct0 wr0 output setting not required pmcct0 = 1 ? ? pct1 wr1 output setting not required pmcct1 = 1 ? ? pct4 rd output setting not required pmcct4 = 1 ? ? pct6 astb output setting not required pmcct6 = 1 ? ? note set pm12n to 1 to use the alternate function of p12n (anin). remark the port register (pn) does not have to be set when the alternate function is used. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 165 table 4-25. register settings to use po rt pins as alternate-function pins (7/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) pdl0 ad0 i/o setting not required pmcdl0 = 1 ? ? pdl1 ad1 i/o setting not required pmcdl1 = 1 ? ? pdl2 ad2 i/o setting not required pmcdl2 = 1 ? ? pdl3 ad3 i/o setting not required pmcdl3 = 1 ? ? pdl4 ad4 i/o setting not required pmcdl4 = 1 ? ? ad5 i/o setting not required pmcdl5 = 1 ? ? pdl5 flmd1 input setting not required setting not required ? ? note pdl6 ad6 i/o setting not required pmcdl6 = 1 ? ? pdl7 ad7 i/o setting not required pmcdl7 = 1 ? ? pdl8 ad8 i/o setting not required pmcdl8 = 1 ? ? pdl9 ad9 i/o setting not required pmcdl9 = 1 ? ? pdl10 ad10 i/o setting not required pmcdl10 = 1 ? ? pdl11 ad11 i/o setting not required pmcdl11 = 1 ? ? pdl12 ad12 i/o setting not required pmcdl12 = 1 ? ? pdl13 ad13 i/o setting not required pmcdl13 = 1 ? ? pdl14 ad14 i/o setting not required pmcdl14 = 1 ? ? pdl15 ad15 i/o setting not required pmcdl15 = 1 ? ? note the flmd1 pin does not have to be manipulated by using a port control register becaus e it is used in the flash programming mode. for details, see chapter 24 flash memory . remark the port register (pn) does not have to be set when the alternate function is used. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 166 4.4 block diagrams of port figure 4-2. block diagram of type a-1 address rd a/d input signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector chapter 4 port functions preliminary user?s manual u17717ej2v0ud 167 figure 4-3. block diagram of type b-1 rd wr pm pmmn wr port pmn pmn internal bus selector selector address chapter 4 port functions preliminary user?s manual u17717ej2v0ud 168 figure 4-4. block diagram of type c-1 address rd wr port pmn wr pu pumn wr pm pmmn pmn p-ch internal bus selector selector chapter 4 port functions preliminary user?s manual u17717ej2v0ud 169 figure 4-5. block diagram of type d-1 wr port pmn wr pm pmmn wr pmc pmcmn rd input signal when alternate function is used pmn internal bus selector selector address chapter 4 port functions preliminary user?s manual u17717ej2v0ud 170 figure 4-6. block diagram of type d-2 wr port pmn wr pm pmmn wr pmc pmcmn rd output signal when alternate function is used pmn internal bus selector selector selector address chapter 4 port functions preliminary user?s manual u17717ej2v0ud 171 figure 4-7. block diagram of type d-3 wr port pmn wr pm pmmn wr pmc pmcmn rd pmn output signal when alternate function is used input signal when alternate function is used output enable signal of address/data bus input enable signal of address data bus output buffer off signal internal bus selector selector selector selector address chapter 4 port functions preliminary user?s manual u17717ej2v0ud 172 figure 4-8. block diagram of type e-1 address input signal when alternate function is used rd wr port pmn wr pmc pmcmn wr pu pumn wr pm pmmn pmn note ev dd p-ch internal bus selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 173 figure 4-9. block diagram of type e-2 address rd wr port pmn wr pmc pmcmn wr pu pumn wr pm pmmn pmn ev dd p-ch output signal when alternate function is used internal bus selector selector selector chapter 4 port functions preliminary user?s manual u17717ej2v0ud 174 figure 4-10. block diagram of type e-3 address rd wr port pmn wr pmc pmcmn wr pu pumn wr pm pmmn pmn note ev dd p-ch output enable signal when alternate function is used output signal when alternate function is used input signal when alternate function is used internal bus selector selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 175 figure 4-11. block diagram of type g-1 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn pmn note ev dd p-ch output signal when alternate function is used input signal when alternate function is used internal bus selector selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 176 figure 4-12. block diagram of type g-2 address rd wr port pmn wr pmc pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn pmn input signal when on-chip debugging note ev dd p-ch on-chip debug mode signal input signal when alternate function is used internal bus selector selector noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 177 figure 4-13. block diagram of type g-3 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn pmn ev dd p-ch output signal when alternate function is used internal bus selector selector selector chapter 4 port functions preliminary user?s manual u17717ej2v0ud 178 figure 4-14. block diagram of type g-4 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn pmn note ev dd p-ch input signal when alternate function is used internal bus selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 179 figure 4-15. block diagram of type g-5 address rd wr port pmn wr pfc pfcmn wr pmc pmcmn wr pm pmmn pmn note wr pu pumn ev dd p-ch output signal when alternate function is used output enable signal when alternate function is used input signal when alternate function is used internal bus selector selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 180 figure 4-16. block diagram of type l-1 address rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pu pumn wr pm pmmn pmn note 2 ev dd p-ch input signal when alternate function is used internal bus selector selector edge detection noise elimination notes 1. see 16.6 external interrupt request input pins (nmi and intp0 to intp14) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 181 figure 4-17. block diagram of type l-2 address rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pu pumn wr pm pmmn pmn note 2 ev dd p-ch input signal 1-1 when alternate function is used input signal 1-2 when alternate function is used internal bus selector selector edge detection noise elimination notes 1. see 16.6 external interrupt request input pins (nmi and intp0 to intp14) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 182 figure 4-18. block diagram of type n-1 address rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pu pumn wr pm wr pfc pfcmn pmmn pmn note 2 ev dd p-ch input signal 1 when alternate function is used input signal 2 when alternate function is used internal bus selector selector edge detection noise elimination selector notes 1. see 16.6 external interrupt request input pins (nmi and intp0 to intp14) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 183 figure 4-19. block diagram of type n-2 address rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pu pumn wr pm wr pfc pfcmn pmmn pmn note 2 ev dd p-ch input signal when alternate function is used internal bus selector selector edge detection noise elimination notes 1. see 16.6 external interrupt request input pins (nmi and intp0 to intp14) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 184 figure 4-20. block diagram of type u-4 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn pmn wr pfce pfcemn note ev dd p-ch input signal 1-1 when alternate function is used output signal when alternate function is used input signal 1-2 when alternate function is used internal bus selector selector selector noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 185 figure 4-21. block diagram of type u-5 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn pmn wr pfce pfcemn note ev dd p-ch output signal when alternate function is used on-chip debug mode signal internal bus selector selector selector input signal 1-2 when alternate function is used input signal when on-chip debugging input signal 1-1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 186 figure 4-22. block diagram of type u-6 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn wr pfce pfcemn note ev dd p-ch pmn output signal when alternate function is used output signal when on-chip debugging on-chip debug mode signal internal bus selector selector selector selector input signal 1-2 when alternate function is used input signal 1-1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 187 figure 4-23. block diagram of type u-7 address rd wr port wr pmc pmmn pfcemn pfcmn wr pu pumn wr pm wr pfc wr pfce pmcmn pmn pmn note ev dd p-ch internal bus selector selector selector input signal 2-1 when alternate function is used input signal 2-2 when alternate function is used input signal 1 when alternate function is used noise elimination noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 188 figure 4-24. block diagram of type u-8 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn pmn wr pfce pfcemn note ev dd p-ch internal bus selector selector selector selector input signal 2 when alternate function is used input signal 1 when alternate function is used output signal when alternate function is used note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 189 figure 4-25. block diagram of type u-9 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn pmn wr pfce pfcemn note ev dd p-ch internal bus selector selector selector input signal when alternate function is used output signal when alternate function is used note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 190 figure 4-26. block diagram of type u-11 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn wr pfce pfcemn note pmn ev dd p-ch internal bus selector selector selector input signal when alternate function is used output signal when alternate function is used note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 191 figure 4-27. block diagram of type u-12 address rd wr port pmn wr pfc pfcmn wr pu pumn wr pmc pmcmn wr pm pmmn wr pfce pfcemn note pmn ev dd p-ch input signal when alternate function is used output signal when alternate function is used internal bus selector selector selector noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 192 figure 4-28. block diagram of type u-13 address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn wr pfce pfcemn note pmn ev dd p-ch input signal 1 when alternate function is used input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used internal bus selector selector selector selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 193 figure 4-29. block diagram of type w-1 address rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn wr pfce pfcemn pmmn note 2 pmn ev dd p-ch input signal when alternate function is used output signal when alternate function is used internal bus selector selector selector edge detection noise elimination notes 1. see 16.6 external interrupt request input pins (nmi and intp0 to intp14) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 194 figure 4-30. block diagram of type aa-1 address reset signal by poc on-chip debug mode signal rd wr port pmn wr intf intfmn note 1 wr pu pumn wr pmc pmcmn wr pm pmmn n-ch wr intr intrmn note 1 ev ss note 2 pmn ev dd p-ch input signal when on-chip debugging input signal when alternate function is used internal bus selector selector edge detection noise elimination notes 1. see 16.6 external interrupt request input pins (nmi and intp0 to intp14) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions preliminary user?s manual u17717ej2v0ud 195 4.5 cautions 4.5.1 cautions on setting port pins (1) in the v850es/hj2, the general-pur pose port function and several peripheral function i/o pin share a pin. to switch between the genera l-purpose port (port mode) an d the peripheral function i/o pin (alternate-function mode), set by the pmcn register. in regards to this register setting sequence, note with caution the following. (a) cautions on switching from por t mode to alternate-function mode to switch from the port mode to alternat e-function mode in the following order. <1> set the pfn register note : n-ch open-drain setting <2> set the pfcn and pfcen regist ers: alternate-function selection <3> set the corresponding bit of the pmcn regist er to 1: switch to alternate-function mode if the pmcn register is set first, not e with caution that, at that moment or depending on the change of the pin states in accordance with the setting of the pf n, pfcn, and pfcen register s, unexpected operations may occur. note n-ch open-drain output pin only caution regardless of the port mo de/alternate-function mode, the pn register is read and written as follows. ? pn register read: read the port output latc h value (when pmn.pmnm bit = 0), or read the pin states (pmn.pmnm bit = 1). ? pn register write: write to the port output latch preliminary user?s manual u17717ej2v0ud 196 chapter 5 bus control function the v850es/hj2 is provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 5.1 features multiplexed bus with a minimum of 3 bus cycles 8-bit/16-bit data bus selectable wait function ? programmable wait function of up to 7 states ? external wait function using wait pin idle state function bus hold function external devices can be connected using alternate-function port pins misaligned access possible chip select function (4 spaces) chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 197 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control cs0 to cs3 pcs0 to pcs3 output chip select 5.2.1 pin status when internal rom, intern al ram, or on-chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o are accessed, the status of each pin is as follows. table 5-2. pin statuses when in ternal rom, internal ram, or on-chip peripheral i/o is accessed address/data bus (ad15 to ad0) undefined control signal inactive caution when a write access is perfo rmed to the internal rom area, address, data, and control signals are activated in the same way as acce ss to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850es/hj2 in each operation mode, see 2.2 pin status . chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 198 5.3 memory block function the 256 kb external memory space is divided into memory blocks of (lower) 64 kb, 64 kb, 64 kb, and 64 kb. the programmable wait function and bus cycl e operation mode for each of these bloc ks can be independen tly controlled in one-block units. figure 5-1. data memory map: physical address cs3 cs2 cs1 cs0 (80 kb) use prohibited use prohibited use prohibited use prohibited external memory area (64 kb) internal rom area note 2 (1 mb) external memory area (64 kb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) external memory area (64 kb) external memory area (64 kb) (2 mb) 03ffffffh 03fec000h 03febfffh 00810000h 0080ffffh 00800000h 007fffffh 00400000h 003fffffh 00410000h 0040ffffh 00200000h 001fffffh 00210000h 0020ffffh 00000000h 03ffffffh 03fff000h 03ffefffh 001fffffh 00100000h 000fffffh 00110000h 0010ffffh 00000000h use prohibited note 1 03ff0000h 03feffffh 03fec000h notes 1. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. this area is an external memory area in the case of a data write access. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 199 5.4 bus access 5.4.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 3 + n instruction fetch (branch) 2 2 note 3 + n operand data access 3 1 3 + n note increases by 1 if a conflict with a data access occurs. remark unit: clocks/access 5.4.2 bus size setting function each external memory area selected by csn can be set by using the bsc register. however, the bus size can be set to 8 bits and 16 bits only. the external memory area of the v850 es/hj2 is selected by cs0 to cs3. (1) bus size configuration register (bsc) the bsc register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, an d then do not change the set values. also, do not access an external memory area until the initial settings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 cs1 caution be sure to set bits 14, 12, 10, and 8 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 200 5.4.3 access by bus size the v850es/hj2 accesses the on-chip peripheral i/o and external memory in 8-bit, 16-bit, or 32- bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is descr ibed below. all data is accessed starting from the lower side. the v850es/hj2 supports only the little-endian format. figure 5-2. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/hj2 has an address misalign function. with this function, data can be placed at all addresse s, regardless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 201 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 202 (3) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 203 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 204 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 205 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 206 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 207 5.5 wait function 5.5.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be pr ogrammed by using the dwc0 register . immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. reset sets this register to 7777h. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-ch ip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, a nd then do not change the set values. also, do not access an external memory area until the in itial settings of the dwc0 register are complete. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 not inserted 1 2 3 4 5 6 7 dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 cs1 caution be sure to clear bits 15, 11, 7, and 3 to ?0?. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 208 5.5.2 external wait function to synchronize an extremely slow external memory, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). when the pcm0 pin is set to alternate function, the external wait function is enabled. access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. 5.5.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specifi ed by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait an d the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. inserting wait example clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 209 5.5.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the awc register. address wait insertion is set for each chip select area (cs0 to cs3). if an address setup wait is inserted, it seems that the high-clock period of the t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low-cl ock period of the t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. address setup wait and address hold wa it cycles are not inserted when the internal rom area, internal ram area, and on-ch ip peripheral i/o areas are accessed. 2. write to the awc register after reset, a nd then do not change the set values. also, do not access an external memory area until the initial settings of the awc register are complete. after reset: ffffh r/w address: fffff488h 1 ahw3 awc 1 asw3 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address setup wait (n = 0 to 3) cs0 cs3 cs2 cs1 ahwn 0 1 not inserted inserted specifies insertion of address hold wait (n = 0 to 3) caution be sure to set bits 15 to 8 to ?1?. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 210 5.6 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted a fter the t3 state in the bus cycle that is executed for each space select ed by the chip select function. by in serting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) the bcc register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted i nserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 cs1 caution be sure to set bits 15, 13, 11, and 9 to ?1?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 211 5.7 bus hold function 5.7.1 functional outline the hldrq and hldak functions are valid if the pc m2 and pcm3 pins are set in the control mode. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until an on-chip peripheral i/o register or t he external memory is accessed. the bus hold status is indicated by assertion of the hldak pin (low level). the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-acce ss cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 212 5.7.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.7.3 operation in power save mode because the internal system clock is stopped in the stop , idle1, and idle2 modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deassert ed, the hldak pin is also deasserted, and the bus hold status is cleared. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 213 5.8 bus priority bus hold, dma transfer, operand data accesses, instructio n fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. bus hold has the highest priority, followed by dma trans fer, operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-3. bus priority priority external bus cycle bus master bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 214 5.9 bus timing figure 5-4. bus read timing (b us size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout astb cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-5. bus read timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 215 figure 5-6. bus write timing (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout astb cs3 to cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active figure 5-7. bus write timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 wr1, wr0 chapter 5 bus control function preliminary user?s manual u17717ej2v0ud 216 figure 5-8. bus hold timing (b us size: 16 bits, 16-bit access) t1 a1 t2 t3 ti note th th th th ti note t1 t2 t3 d1 clkout hldrq hldak astb cs3 to cs0 ad15 to ad0 rd undefined undefined a2 d2 1111 1111 note this idle state (ti) does not de pend on the bcc register settings. remarks 1. see table 2-4 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. figure 5-9. address wait timing (bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb ad15 to ad0 cs3 to cs0 wait rd a1 t1 t2 clkout astb ad15 to ad0 cs3 to cs0 wait rd d1 d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance. preliminary user?s manual u17717ej2v0ud 217 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. main clock oscillator ? in clock-through mode f x = 4 to 5 mhz (f xx = 4 to 5 mhz) ? in pll mode f x = 4 to 5 mhz (f xx = 16 to 20 mhz) subclock oscillator (crystal oscillation or rc o scillation selectable by option byte function) ? 32.768 khz (crystal resonator) ? 20 khz (rc oscillator) multiply ( 4) function by pll (phase locked loop) ? clock-through mode/pll mode selectable internal oscillator ? f r = 200 khz (typ.) internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) peripheral clock generation clock output function programmable clock (pcl) output function remark f x : main clock oscillation frequency f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 218 6.2 configuration figure 6-1. clock generator frc bit mfrc bit mck bit ck2 to ck0 bits selpll bit pllon bit pck1, pck0 bits cls, ck3 bits stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock timer m clock watch timer clock, watchdog timer 2 clock peripheral clock, watchdog timer 2 clock watchdog timer 2 clock, timer m clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control rstop bit internal oscillator 1/8 divider xt1 xt2 clkout x1 x2 pcl idle mode pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1024 f x to f x /1024 watchdog timer 2 clock f brg = f x /2 to f x /2 12 f xt f xt f xx f x f r f r /8 idle control note prescaler 4 selector selector selector selector selector note the internal oscillation clock is selected when watchdog timer 2 overflows during the oscillation stabilization time. remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f r : internal oscillation clock frequency chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 219 (1) main clock oscillator the main resonator oscillates the following frequencies (f x ). ? in clock-through mode f x = 4 to 5 mhz ? in pll mode f x = 4 to 5 mhz (f xx = 16 to 20 mhz) (2) subclock oscillator the sub-resonator oscillates a frequency (f xt ) of 32.768 khz or 20 khz. (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillat or is stopped in the stop mode or when the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) internal oscillator oscillates a frequency (f r ) of 200 khz (typ.). (5) prescaler 1 this circuit generates the clock (f xx to f xx /1,024) to be supplied to the following on-chip peripheral functions: tmp0 to tmp3, tmq0 to tmq2, tmm0, csib0 to csib2, uarta0 to uarta3 note , adc, and wdt2 note uart3: pd70f3711, 70f3712 only (6) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom, and ram blocks, and can be output from the clkout pin. (7) prescaler 3 this circuit divides the clock generated by the main clock oscillator (f x ) to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, see chapter 10 watch timer functions . (8) prescaler 4 this circuit generates the clock (f x to f x /1,024) to be supplied to on-chip peripheral function. the block to be supplied is wdt2 only. (9) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 4. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be sele cted by using the pllctl.selpll bit. whether the clock is multiplied by 4 is selected by th e ckc.ckdiv0 bit, and pll is started or stopped by the pllctl.pllon bit. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 220 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 221 frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 main clock oscillator control used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) even if the mck bit is set (1) while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. before setting the mck bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. when the main clock is stopped and the device is operating with the subclock, clear (0) the mck bit and secure the oscillation stabilization time by software before switching the cpu clock to the main clock or operating the on-chip peripheral functions. f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 note the cls bit is a read-only bit. cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. remark : don?t care chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 222 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if subclock operation has started. it takes the following time after the ck3 bit is se t until subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping the ma in clock, stop the pll. also stop the operations of the on-chip peripheral functions operati ng with the main clock. 2. if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped. _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <2> above, the cls bit is read in a closed loop. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 223 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 0: use of a bit manipulation instruction is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time after the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one nop instructi on immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. caution enable operation of the on-chip peripher al functions operating with the main clock only after the oscillation of the main clock stabilizes. if their operations are enabled before the lapse of the oscillation stabilizat ion time, a malfunction may occur. [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating. <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time. _wait_ost : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _wait_ost <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts. bnz _check_cls _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <4> above, the cls bit is read in a closed loop. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 224 (2) internal oscillati on mode register (rcm) the rcm register is an 8-bit register that sets the operation mode of the internal oscillator. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 rcm 0 0 0 00 0 rstop internal oscillator oscillation internal oscillator stopped rstop 0 1 oscillation/stop of internal oscillator after reset: 00h r/w address: fffff80ch cautions 1. the settings of the rcm regi ster are valid by se tting the option byte. for details, see chapter 25 option byte function. 2. the internal oscillator cannot be stoppe d while the cpu is operating on the internal oscillation clock (ccls.cclsf bit = 1). do not set the rstop bit to 1. 3. the internal oscillator o scillates if the ccls.cclsf bit is set to 1 (when wdt overflow occurs during oscillation stabilizat ion) even when the rstop bit is set to 1. at this time, the rstop bit remains being set to 1. (3) cpu operation clock status register (ccls) the ccls register indicates the stat us of the cpu operation clock. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h note r address: fffff82eh operating on main clock (f x ) or subclock (f xt ). operating on internal oscillation clock (f r ). cclsf 0 1 cpu operation clock status note if wdt overflow occurs during oscillation stabilization after a reset is releas ed, the cclsf bit is set to 1 and the reset value is 01h. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 225 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle1, idle2 mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) subclock oscillator (f xt ) cpu clock (f cpu ) internal system clock (f clk ) main clock (in pll mode, f xx ) note 1 note 2 peripheral clock (f xx to f xx /1,024) wt clock (main) wt clock (sub) wdt2 clock (internal oscillation) wdt2 clock (main) notes 1. oscillation starts after time 1/2 of the oscillation stabilization time, and the stable clock is supplied after lockup time. 2. operable in the idle1 mode. stopped in the idle2 mode. remark : operable : stopped 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alte rnately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the in ternal system clock in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped stat us. however, the clkout pin is in the port mode (pcm1 pin: input mode) after reset and until it is set in the output mode. ther efore, the stat us of the pin is hi-z. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 226 6.5 pll function 6.5.1 overview in the v850es/hj2, an operating clock that is 4 times higher than the oscillation fr equency output by the pll function or the clock-through mode can be selected as the operating clock of the cpu and on-chip peripheral functions. when pll function is used: input clock = 4 to 5 mhz (output: 16 to 20 mhz) clock-through mode: input clock = 4 to 5 mhz (output: 4 to 5 mhz) 6.5.2 registers (1) pll control register (pllctl) the pllctl register is an 8-bit regi ster that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon pll stopped pll operating (after pll operation starts, a lockup time is required for frequency stabilization) pllon 0 1 pll operation stop register clock-through mode pll mode selpll 0 1 cpu operation clock selection register after reset: 01h r/w address: fffff82ch cautions 1. when the pllon bit is cleared to 0, the selpll bit is automatically cleared to 0 (clock- through mode). 2. the selpll bit can be set to 1 only when the pll clock frequency is stabilized. if not (unlocked), ?0? is written to the sel pll bit if data is written to it. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 227 (2) lock register (lockr) phase lock occurs at a given frequency following powe r application or immediately after the stop mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). this state until stabilization is called the lock up status, and the stabilized state is called the locked status. the lockr register includes a lock bit that re flects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h caution the lock register does not reflect the lock status of the p ll in real time. the set/clear conditions are as follows. [set conditions] ? upon system reset note ? in idle2 or stop mode ? upon setting of pll stop (clearing of pllctl.pllon bit to 0) ? upon stopping main clock and using cpu with subc lock (setting of pcc.ck3 bit to 1 and setting of pcc.mck bit to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [clear conditions] ? upon overflow of oscillation stabilization time fo llowing reset release (osts register default time (see 18.2 (3) oscillation stabilization time select register (osts) )) ? upon oscillation stabilization timer overflow (tim e set by osts register) following stop mode release, when the stop mode was set in the pll operating status ? upon pll lockup time timer overflow (time set by plls register) when the pllctl.pllon bit is changed from 0 to 1 ? after the setup time inserted upon release of the id le2 mode is released (time set by the osts register) when the idle2 mode is set during pll operation. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 228 (3) pll lockup time specification register (plls) the plls register is an 8-bit register used to sele ct the pll lockup time when the pllctl.pllon bit is changed from 0 to 1. this register can be read or written in 8-bit units. reset sets this register to 03h. 0 2 10 /f x 2 11 f x 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h cautions 1. set so that the lockup time is 800 s or longer. 2. do not change the plls regi ster setting during the lockup period. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 229 (4) programmable clock mode register (pclm) the pclm register is an 8-bit regi ster used to control the pcl output. this register can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff82fh 0 pcle 0 1 pcl pin output disabled (pcl pin is fixed to low level) pcl pin output enabled selection of pcl pin output operation pclm 0 0 pcle 0 0 pck1 pck0 caution set the port-related control re gisters (pm, pmc, pfc, and pfce registers, etc.) first, and then set the pcle bit to 1. f xx /2 f xx /4 f xx /8 f xx /16 pck1 0 0 1 1 pck0 0 1 0 1 selection of pll output clock caution set the pcle bit to 1 only during pll operati on. to stop the pll, clear the pcle bit to 0. chapter 6 clock generation function preliminary user?s manual u17717ej2v0ud 230 6.5.3 usage (1) when pll is used ? after the reset signal has been released, the pll operates (pllctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bi t = 0), select the pll mode (selpll bit = 1). ? to enable pll operation, first set the pllon bit to 1, and then set the selpll bit to 1 after the lockr.lock bit = 0. to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). ? the pll stops during transition to idle2 or stop m ode regardless of the setting and is restored from idle2 or stop mode to the status before transition. the time requir ed for restoration is as follows. (a) when transiting to idle2 or stop mode from the clock through mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 350 s (min.) or longer. (b) when shifting to the idle 2 or stop mode while remaining in the pll operation mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 800 s (min.) or longer. when shifting to the idle1 mode, the pll does not stop. stop the pll if necessary. (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected a fter the reset signal has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0). preliminary user?s manual u17717ej2v0ud 231 chapter 7 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850es/hj2 has four timer/event counter channels, tmp0 to tmp3. 7.1 overview an outline of tmpn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 remark n = 0 to 3 7.2 functions tmpn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 232 7.3 configuration tmpn includes the following hardware. table 7-1. configuration of tmpn item configuration timer register 16-bit counter registers tmpn capture/compare re gisters 0, 1 (tpnccr0, tpnccr1) tmpn counter read buffer register (tpncnt) ccr0, ccr1 buffer registers timer inputs 2 (tipn0 note 1 , tipn1 pins) timer outputs 2 (topn0, topn1 pins) control registers note 2 tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option register 0 (tpnopt0) notes 1. the tipn0 pin functions alternately as a capt ure trigger input signal, external event count input signal, and external trigger input signal. 2. when using the functions of the tip n0, tipn1, topn0, and topn1 pins, see table 4-25 using port pin as alternate-function pin . remark n = 0 to 3 figure 7-1. block diagram of tmpn f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 note 1 , f xt note 2 selector internal bus internal bus topn0 topn1 tipn0 tipn1 selector edge detector ccr0 buffer register ccr1 buffer register tpnccr0 tpnccr1 16-bit counter tpncnt inttpnov inttpncc0 inttpncc1 output controller clear notes 1. tmp0, tmp2 2. tmp1, tmp3 (counting operation cannot be perfo rmed with the subclock when the main clock is stopped.) remark f xx : main clock frequency f xt : subclock frequency chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 233 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tpncnt register. when the tpnctl0.tpnce bit = 0, the va lue of the 16-bit counter is ffffh. if the tpncnt register is read at this time, 0000h is read. reset sets the tpnce bit to 0. therefor e, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr0 register is used as a compare regist er, the value written to the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tpnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr1 register is used as a compare regist er, the value written to the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tpnccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tipn0 and tipn1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tpnioc1 and tpnioc2 registers. (5) output controller this circuit controls the output of the topn0 and topn 1 pins. the output contro ller is controlled by the tpnioc0 register. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 234 7.4 registers the registers that control tmpn are as follows. ? tmpn control register 0 (tpnctl0) ? tmpn control register 1 (tpnctl1) ? tmpn i/o control register 0 (tpnioc0) ? tmpn i/o control register 1 (tpnioc1) ? tmpn i/o control register 2 (tpnioc2) ? tmpn option register 0 (tpnopt0) ? tmpn capture/compare register 0 (tpnccr0) ? tmpn capture/compare register 1 (tpnccr1) ? tmpn counter read buffer register (tpncnt) remarks 1. when using the functions of the tip n0, tipn1, topn0, and topn1 pins, see table 4-25 using port pin as alternate-function pin . 2. n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 235 (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tpnctl0 register by software. tpnce tmpn operation disabled (tmpn reset asynchronously note 1 ). tmpn operation enabled. tmpn operation started. tpnce 0 1 tmpn operation control tpnctl0 (n = 0 to 3) 0 0 0 0 tpncks2 tpncks1 tpncks0 654321 after reset: 00h r/w address: tp0ctl0 fffff590h, tp1ctl0 fffff5a0h, tp2ctl0 fffff5b0h, tp3ctl0 fffff5c0h 7 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xt note 2 tpncks2 0 0 0 0 1 1 1 1 internal count clock selection n = 0, 2 n = 1, 3 tpncks1 0 0 1 1 0 0 1 1 tpncks0 0 1 0 1 0 1 0 1 notes 1. tpn0pt0.tpnovf bit, 16-bit counter, timer output (topn0, topn1 pins) 2. counting operation cannot be performed with the subclock when the main clock is stopped. cautions 1. set the tpncks2 to tpncks0 bits when the tpnce bit = 0. when the value of the tpnce bi t is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency f xt : subclock frequency chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 236 (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) tpnsye tpnest 0 1 software trigger control slave timer tpnctl1 (n = 0 to 3) tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 654321 after reset: 00h r/w address: tp0ctl1 fffff591h, tp1ctl1 fffff5a1h, tp2ctl1 fffff5b1h, tp3ctl1 fffff5c1h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tpnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tpnest bit as the trigger. 7 0 ? tpnsye 0 1 tuned operation mode enable control tuned operation mode (specification of slave operation) in this mode, timer p can operate in synchronization with a master timer. independent operation mode (asynchronous operation mode) for the tuned operation mode, see 7.6 timer tuned operation function . caution be sure to clear the tp0sye and tp2sye bits to 0. master timer tmp0 tmp2 tmq1 tmp1 tmp3 tmq2 ? tmq0 ? cautions 1. the tpnest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. be sure to clear bits 3 and 4 to ?0?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 237 (2/2) disable operation with external event count input. (perform counting with the count clock selected by the tpnctl0.tpnck0 to tpnck2 bits.) tpneee 0 1 count clock selection the tpneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tpnmd2 0 0 0 0 1 1 1 1 timer mode selection tpnmd1 0 0 1 1 0 0 1 1 tpnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) cautions 1. external event count input is selected in the external event count mode regardless of the value of the tpneee bit. 2. set the tpneee and tpnmd2 to tpnmd0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) the operation is not guaranteed when rewr iting is performed with the tpnce bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 238 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnol1 0 1 topn1 pin output level setting topn1 pin output inversion disabled topn1 pin output inversion enabled tpnioc0 (n = 0 to 3) 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 654321 after reset: 00h r/w address: tp0ioc0 fffff592h, tp1ioc0 fffff5a2h, tp2ioc0 fffff5b2h, tp3ioc0 fffff5c2h tpnoe1 0 1 topn1 pin output setting timer output disabled ? when tpnol1 bit = 0: low level is output from the topn1 pin ? when tpnol1 bit = 1: high level is output from the topn1 pin tpnol0 0 1 topn0 pin output level setting topn0 pin output inversion disabled topn0 pin output inversion enabled tpnoe0 0 1 topn0 pin output setting timer output disabled ? when tpnol0 bit = 0: low level is output from the topn0 pin ? when tpnol0 bit = 1: high level is output from the topn0 pin 7 0 timer output enabled (a square wave is output from the topn1 pin). timer output enabled (a square wave is output from the topn0 pin). cautions 1. rewrite the tpnol1, tpnoe1, tpnol0, and tpnoe0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. even if the tpnolm bit is manipulated when the tpnce and tpnoem bits are 0, the topnm pin output level varies (m = 0, 1). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 239 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit regist er that controls the valid edge of the capture trig ger input signals (tipn0, tipn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnis3 0 0 1 1 tpnis2 0 1 0 1 capture trigger input signal (tipn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tpnioc1 (n = 0 to 3) 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 654321 after reset: 00h r/w address: tp0ioc1 fffff593h, tp1ioc1 fffff5a3h, tp2ioc1 fffff5b3h, tp3ioc1 fffff5c3h tpnis1 0 0 1 1 tpnis0 0 1 0 1 capture trigger input signal (tipn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 240 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tipn0 pin) and external trigger input signal (tipn0 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnees1 0 0 1 1 tpnees0 0 1 0 1 external event count input signal (tipn0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tpnioc2 (n = 0 to 3) 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 654321 after reset: 00h r/w address: tp0ioc2 fffff594h, tp1ioc2 fffff5a4h, tp2ioc2 fffff5b4h, tp3ioc2 fffff5c4h tpnets1 0 0 1 1 tpnets0 0 1 0 1 external trigger input signal (tipn0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnees1, tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or when the external event count mode (tpnctl1.tpnmd 2 to tpnctl1.tpnmd0 bits = 001) has been set. 3. the tpnets1 and tpnets0 bits are valid only when the external trigger pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 010) or the one-shot pulse output mode (tpnctl1.tpn md2 to tpnctl1.tpnmd0 = 011) is set. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 241 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnccs1 0 1 tpnccr1 register capture/compare selection the tpnccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tpnopt0 (n = 0 to 3) 0 tpnccs1 tpnccs0 0 0 0 tpnovf 654321 after reset: 00h r/w address: tp0opt0 fffff595h, tp1opt0 fffff5a5h, tp2opt0 fffff5b5h, tp3opt0 fffff5c5h tpnccs0 0 1 tpnccr0 register capture/compare selection the tpnccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tpnovf set (1) reset (0) tmpn overflow detection flag the tpnovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. an interrupt request signal (inttpnov) is generated at the same time that the tpnovf bit is set to 1. the inttpnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. the tpnovf bit is not cleared even when the tpnovf bit or the tpnopt0 register are read when the tpnovf bit = 1. the tpnovf bit can be both read and written, but the tpnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmpn. overflow occurred tpnovf bit 0 written or tpnctl0.tpnce bit = 0 7 0 cautions 1. rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mi stakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to ?0?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 242 (7) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs0 bit. in the pulse width measurement mode, the tpnccr0 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tpnccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr0 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpnccr0 (n = 0 to 3) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr0 fffff596h, tp1ccr0 fffff5a6h, tp2ccr0 fffff5b6h, tp3ccr0 fffff5c6h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 243 (a) function as compare register the tpnccr0 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. if topn0 pin output is ena bled at this time, the output of the topn0 pin is inverted. when the tpnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. (b) function as capture register when the tpnccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr0 register if the valid ed ge of the capture trigger input pin (tipn0 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tpnccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn0) is detected. even if the capture operation and reading the tpn ccr0 register conflict, the correct value of the tpnccr0 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 244 (8) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs1 bit. in the pulse width measurement mode, the tpnccr1 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tpnccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr1 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpnccr1 (n = 0 to 3) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr1 fffff598h, tp1ccr1 fffff5a8h, tp2ccr1 fffff5b8h, tp3ccr1 fffff5c8h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 245 (a) function as compare register the tpnccr1 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. if topn1 pin output is ena bled at this time, the output of the topn1 pin is inverted. (b) function as capture register when the tpnccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr1 register if the valid ed ge of the capture trigger input pin (tipn1 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tpnccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn1) is detected. even if the capture operation and reading the tpn ccr1 register conflict, the correct value of the tpnccr1 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 246 (9) tmpn counter read bu ffer register (tpncnt) the tpncnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tpnctl0.tpnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tpncnt register is cleared to 0000h when the tpnce bit = 0. if the tpncnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tpncnt register is cleared to 000 0h after reset, as the tpnce bit is cleared to 0. caution accessing the tpncnt register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpncnt (n = 0 to 3) 12 10 8 6 4 2 after reset: 0000h r address: tp0cnt fffff59ah, tp1cnt fffff5aah, tp2cnt fffff5bah, tp3cnt fffff5cah 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 247 (10) tipnm pin noise eliminatio n control register (pnmnfc) the pnmnfc register is an 8-bit regist er that sets the digital noise filter of the timer p input pin for noise elimination. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: p00nfc : fffffb00h (tip00 pin) p01nfc : fffffb04h (tip01 pin) p10nfc : fffffb08h (tip10 pin) p11nfc : fffffb0ch (tip11 pin) p20nfc : fffffb10h (tip20 pin) p21nfc : fffffb14h (tip21 pin) p30nfc : fffffb18h (tip30 pin) p31nfc : fffffb1ch (tip31 pin) 7 6 5 4 3 2 1 0 pnmnfc 0 nfsts 0 0 0 nfc2 nfc1 nfc0 (n = 0 to 3, m = 0, 1) nfsts setting of number of times of sampling by digital noise filter 0 3 times 1 2 times sampling clock nfc2 nfc1 nfc0 n = 0, 2 n = 1, 3 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /16 f xx /8 1 0 0 f xx /32 f xx /16 1 0 1 f xx /64 f xt other than above setting prohibited cautions 1. be sure to clea r bits 3 to 5 and 7 to ?0?. 2. a signal input to the timer input pin (tipnm) before the pnmnfc register is set is output wi th digital noise eliminated. therefore, set the sampling clock (nfc2 to nfc0) and the number of times of sampling (nfsts) by using the pnmnfc register, wait for initialization time = (sampling clock) (number of times of sampling), and enable the timer operation. remark the width of the noise that can be accu rately eliminated is (sampling clock) (number of times of sampling ? 1). even noise with a width narrower than this may cause a miscount if it is synchronized with the sampling clock. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 248 7.5 operation tmpn can perform the following operations. operation tpnctl1.tpnest bit (software trigger bit) tipn0 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that t he valid edge of the tipn0 pin capture trigger input is not detected (by clearing the tpnioc1.tpni s1 and tpnioc1.tpnis0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tpnctl1.tpneee bit to 0). remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 249 7.5.1 interval timer mode (t pnmd2 to tpnmd0 bits = 000) in the interval timer mode, an interrupt request signal (inttpncc0) is generated at t he specified interval if the tpnctl0.tpnce bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the topn0 pin. usually, the tpnccr1 register is not used in the interval timer mode. figure 7-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tpnce bit tpnccr0 register count clock selection clear match signal topn0 pin inttpncc0 signal remark n = 0 to 3 figure 7-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 250 when the tpnce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the topn0 pin is inverted. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, the output of the topn0 pin is in verted, and a compare match interrupt request signal (inttpncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tpnccr0 register + 1) count clock cycle remark n = 0 to 3 figure 7-4. register setting for in terval timer mode operation (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 note 00 tpnctl1 0, 0, 0: interval timer mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event count input signal 000 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tpnsye note this bit can be set to 1 only when the interrupt request signals (inttpncc0 and inttpncc1) are masked by the interrupt mask flags (tpnccmk0 and tpnccmk1) and timer output (topn1) is performed at the same time. however, set the tp nccr0 and tpnccr1 registers to the same value (see 7.5.1 (2) (d) operation of tpnccr1 register ). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 251 figure 7-4. register setting for in terval timer mode operation (2/2) (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level with operation of topn0 pin disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level with operation of topn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn counter read bu ffer register (tpncnt) by reading the tpncnt register, the count va lue of the 16-bit counter can be read. (e) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmpn capture/compare register 1 (tpnccr1) usually, the tpnccr1 register is not used in the inte rval timer mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register. a compare match interrupt request signal (inttpncc1) is generated when the count value of th e 16-bit counter matches the value of the ccr1 buffer register. therefore, mask the interrupt request by using the corresponding interrupt mask flag (tpnccmk1). remarks 1. tmpn i/o control register 1 (tpnioc1), tmpn i/o control register 2 (tpnioc2), and tmpn option register 0 (tpnopt0) are not used in the interval timer mode. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 252 (1) interval timer mode operation flow figure 7-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 <1> <2> tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnccr0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 253 (2) interval timer mode operation timing (a) operation if tpnccr0 re gister is set to 0000h if the tpnccr0 register is set to 0000h, the inttpncc0 signal is generated at each count clock subsequent to the first count clock, and t he output of the topn0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal 0000h interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 254 (b) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. t he counter is cleared to 0000h in synchronization with the next count-up timing. the inttpncc0 signal is generated and the output of the topn0 pin is inverted. at this time, an overflow interrupt request signal (inttpnov) is not generated, nor is the overflow flag (tpnopt0.tpnovf bit) set to 1. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 255 (c) notes on rewriting tpnccr0 register to change the value of the tpnccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register tpnol0 bit topn0 pin output inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0 to 3 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tpnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated and the output of the topn0 pin is inverted. therefore, the inttpncc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 256 (d) operation of tpnccr1 register figure 7-6. configuration of tpnccr1 register ccr0 buffer register tpnccr0 register tpnccr1 register ccr1 buffer register topn0 pin inttpncc0 signal topn1 pin inttpncc1 signal 16-bit counter output controller tpnce bit count clock selection clear match signal output controller match signal remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 257 if the set value of the tpnccr1 register is less than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. at the same time, the output of the topn1 pin is inverted. the topn1 pin outputs a square wave with the sa me cycle as that output by the topn0 pin. figure 7-7. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 258 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the count value of the 16-bit counter does not match the va lue of the tpnccr1 register. consequently, the inttpncc1 signal is not generated, nor is the output of the topn1 pin changed. figure 7-8. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 259 7.5.2 external event count mode (tpnmd2 to tpnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tpnctl0.tpnce bit is set to 1, and an interrupt request si gnal (inttpncc0) is generated each time the specified number of edges have been counted . the topn0 pin cannot be used. usually, the tpnccr1 register is not us ed in the external event count mode. figure 7-9. configuration in external event count mode 16-bit counter ccr0 buffer register tpnce bit tpnccr0 register edge detector clear match signal inttpncc0 signal tipn0 pin (external event count input) remark n = 0 to 3 figure 7-10. basic timing in external event count mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 0 d 0 d 0 d 0 16-bit counter tpnccr0 register inttpncc0 signal external event count input (tipn0 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remarks 1. this figure shows the basic timing when the ri sing edge is specified as the valid edge of the external event count input. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 260 when the tpnce bit is set to 1, the value of the 16-bit counter is clea red from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttpncc0) is generated. the inttpncc0 signal is generated each time the valid e dge of the external event count input has been detected (set value of tpnccr0 register + 1) times. figure 7-11. register setting for operati on in external event count mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 0: stop counting 1: enable counting 000 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 0, 0, 1: external event count mode 001 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tpnsye (c) tmpn i/o control register 0 (tpnioc0) 00000 tpnioc0 0: disable topn0 pin output 0: disable topn1 pin output 000 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 261 figure 7-11. register setting for operati on in external event count mode (2/2) (e) tmpn counter read bu ffer register (tpncnt) the count value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register 0 (tpnccr0) if d 0 is set to the tpnccr0 register, the counter is cleared and a compare match interrupt request signal (inttpncc0) is generated when the nu mber of external event counts reaches (d 0 + 1). (g) tmpn capture/compare register 1 (tpnccr1) usually, the tpnccr1 register is not used in the exte rnal event count mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buff er register. when the count value of the 16-bit counter matches the value of the ccr1 buffer regi ster, a compare match interrupt request signal (inttpncc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (tpnccmk1). remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external event count mode. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 262 (1) external event count mode operation flow figure 7-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 0 d 0 d 0 d 0 <1> <2> tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 263 (2) operation timing in external event count mode cautions 1. in the external event count mode , do not set the tpnccr0 register to 0000h. 2. in the external event count mode, use of th e timer output is disabled. if performing timer output using external event co unt input, set the interval timer mode, and select the operation enabled by the external e vent count input fo r the count clock (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bi ts = 000, tpnctl1.tpneee bit = 1). (a) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit co unter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttpncc0 signal is generated. at this time, the tpnopt0.tpnovf bit is not set. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 264 (b) notes on rewriting the tpnccr0 register to change the value of the tpnccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) remark n = 0 to 3 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tpnccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated. therefore, the inttpncc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 265 (c) operation of tpnccr1 register figure 7-13. configuration of tpnccr1 register ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal inttpncc1 signal edge detector tipn0 pin remark n = 0 to 3 if the set value of the tpnccr1 register is smalle r than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. figure 7-14. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 266 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the inttpncc1 signal is not generated because the count va lue of the 16-bit counte r and the value of the tpnccr1 register do not match. figure 7-15. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 267 7.5.3 external trigger pulse output m ode (tpnmd2 to tpnmd0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an ex ternal trigger input signal is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the topn1 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the topn0 pin. figure 7-16. configuration in external trigger pulse output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller topn1 pin inttpncc1 signal topn0 pin count clock selection count start control edge detector software trigger generation tipn0 pin transfer transfer s r remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 268 figure 7-17. basic timing in exte rnal trigger pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter p waits for a trigger when the tpnc e bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the topn1 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of the topn0 pin is inverted. the topn1 pin outputs a high le vel regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the compare match request signal inttpncc0 is generat ed when the 16-bit counter counts next time after its count value matches the value of the c cr0 buffer register, and the 16-bit count er is cleared to 0000h. the compare match interrupt request signal inttpncc1 is generated when t he count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to the ccrm buffer register when the count value of the 16- bit counter matches the value of the ccrm buffer re gister and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 3, m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 269 figure 7-18. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 1 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0/1 0 0 tpnctl1 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event input signal generate software trigger when 1 is written 010 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 0: external trigger pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output settings of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output specifies active level of topn1 pin output 0: active-high 1: active-low 0/1 0/1 0/1 note 2 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 notes 1. the setting is invalid when the tpnctl1.tpneee bit = 1. 2. clear this bit to 0 when the topn0 pin is not used in the external trigger pulse output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 270 figure 7-18. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external trigger pulse output mode. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 271 (1) operation flow in extern al trigger pulse output mode figure 7-19. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 272 figure 7-19. software processing flow in ex ternal trigger pulse output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). trigger wait status tpnccr1 register write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0 and tpnccr1 register setting change flow setting of tpnccr0 register when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <4> tpnccr0, tpnccr1 register setting change flow only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <3> tpnccr0, tpnccr1 register setting change flow tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 273 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr 1 register after the inttpncc0 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 274 in order to transfer data from the tpnccrm register to the ccrm buffer register, the tpnccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level width to the tpnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the val ue written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clear ing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpn ccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 275 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is generated periodically. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 3 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 276 (c) conflict between trigger detecti on and match with tpnccr1 register if the trigger is detected immediately after the inttp ncc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the topn1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark n = 0 to 3 if the trigger is detected immediately before the inttp ncc1 signal is generated, the inttpncc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the topn1 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 277 (d) conflict between trigger detecti on and match with tpnccr0 register if the trigger is detected immediately after the inttp ncc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the topn1 pin is extended by time from generation of the inttpncc0 signal to trigger detection. 16-bit counter tpnccr0 register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark n = 0 to 3 if the trigger is detected immediately before the inttp ncc0 signal is generated, the inttpncc0 signal is not generated. the 16-bit counter is cleared to 0000h, the topn1 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter tpnccr0 register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 278 (e) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in the external trigger pulse output mode differs from the timing of other inttpncc1 signals; the inttpncc1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 3 usually, the inttpncc1 signal is generated in synch ronization with the next count up, after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the topn1 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 279 7.5.4 one-shot pulse output mode (tpnmd2 to tpnmd0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event counter p starts counting, and outputs a one-shot pulse from the topn1 pin. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the topn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 7-20. configuration in one-shot pulse output mode ccr0 buffer register tpnce bit tpnccr0 register tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) topn1 pin inttpncc1 signal topn0 pin count clock selection count start control edge detector software trigger generation tipn0 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 280 figure 7-21. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) delay (d 1 ) delay (d 1 ) active level width (d 0 ? d 1 + 1) active level width (d 0 ? d 1 + 1) active level width (d 0 ? d 1 + 1) when the tpnce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a one-shot pul se from the topn1 pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-s hot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tpnccr1 register) count clock cycle active level width = (set value of tpnccr0 register ? set value of tpnccr1 register + 1) count clock cycle the compare match interrupt request signal inttpncc0 is generated when the 16-bit counter counts after its count value matches the value of the c cr0 buffer register. the compare match interrupt request signal inttpncc1 is generated when the count value of the 16-bit counter matches the va lue of the ccr1 buffer register. the valid edge of an external trigger input or setting the so ftware trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 281 figure 7-22. setting of registers in one-shot pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 1 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0/1 0 0 tpnctl1 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tpnsye 0, 1, 1: one-shot pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output specifies active level of topn1 pin output 0: active-high 1: active-low 0/1 0/1 note 2 0/1 note 2 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 notes 1. the setting is invalid when the tpnctl1.tpneee bit = 1. 2. clear this bit to 0 when the topn0 pin is not used in the one-shot pulse output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 282 figure 7-22. setting of registers in one-shot pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 1 ? d 0 + 1) count clock cycle output delay period = (d 1 ) count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the one-shot pulse output mode. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 283 (1) operation flow in one-shot pulse output mode figure 7-23. software processing flow in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) <1> <3> tpnce bit = 1 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). trigger wait status start <1> count operation start flow tpnce bit = 0 count operation is stopped stop <3> count operation stop flow d 10 d 00 d 11 d 01 d 00 d 10 d 11 <2> d 01 setting of tpnccr0, tpnccr1 registers as rewriting the tpnccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttpnccr0 signal is recommended. <2> tpnccr0, tpnccr1 register setting change flow remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 284 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tpnccrm register to change the set value of the tpnccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tpnccrm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) delay (d 10 ) active level width (d 00 ? d 10 + 1) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the tpnccr0 register is rewritten from d 00 to d 01 and the tpnccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tpnccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tpnccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter count s up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttpncc1 signal and asserts the topn1 pin. when the count value matches d 01 , the counter generates the in ttpncc0 signal, deasserts the topn1 pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 285 (b) generation timing of compare match interrupt request signal (inttpncc1) the generation timing of the inttpncc1 signal in the one-shot pulse output mode is different from other inttpncc1 signals; the inttpncc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 3 usually, the inttpncc1 signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tpnccr1 register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the topn1 pin. remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 286 7.5.5 pwm output mode (tpnmd 2 to tpnmd0 bits = 100) in the pwm output mode, a pwm waveform is output from the topn1 pin when the tpnctl0.tpnce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the topn0 pin. figure 7-24. configuration in pwm output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller topn1 pin inttpncc1 signal topn0 pin count clock selection count start control transfer transfer s r remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 287 figure 7-25. basic timing in pwm output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ? d 10 + 1) when the tpnce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a pwm waveform from the topn1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the pwm waveform can be changed by rewriting the tpnccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to the ccrm buffer register when the count value of the 16- bit counter matches the value of the ccrm buffer re gister and the 16-bit counter is cleared to 0000h. remark n = 0 to 3, m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 288 figure 7-26. setting of registers in pwm output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 1 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 100 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tpnsye 1, 0, 0: pwm output mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count external event input signal (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output specifies active level of topn1 pin output 0: active-high 1: active-low 0/1 0/1 0/1 note 2 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 notes 1. the setting is invalid when the tpnctl1.tpneee bit = 1. 2. clear this bit to 0 when the topn0 pin is not used in the pwm output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 289 figure 7-26. register setting in pwm output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input. 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the pwm output mode. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 290 (1) operation flow in pwm output mode figure 7-27. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1> remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 291 figure 7-27. software processing flow in pwm output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). tpnccr1 write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0, tpnccr1 register setting change flow setting of tpnccr0 register when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <4> tpnccr0, tpnccr1 register setting change flow only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register m is transferred to the ccrm buffer register. setting of tpnccr1 register <3> tpnccr0, tpnccr1 register setting change flow tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 292 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr 1 register after the inttpncc1 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register tpnccr1 register ccr1 buffer register topn1 pin output inttpncc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tpnccrm register to the ccrm buffer register, the tpnccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level to the tpnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the val ue written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clear ing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpn ccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. remark n = 0 to 3, m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 293 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is generated periodically. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 3 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 294 (c) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in the pwm output mode differs from the timing of other inttpncc1 signals; the inttpncc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 3 usually, the inttpncc1 signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the topn1 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 295 7.5.6 free-running timer mode (t pnmd2 to tpnmd0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. at this time, the tpnccrm register can be used as a compare register or a capt ure register, depending on the setting of the tpnopt0.tpnccs 0 and tpnopt0.tpnccs1 bits. figure 7-28. configuration in free-running timer mode tpnccr0 register (capture) tpnce bit tpnccr1 register (compare) 16-bit counter tpnccr1 register (compare) tpnccr0 register (capture) output controller tpnccs0, tpnccs1 bits (capture/compare selection) topn0 pin output output controller topn1 pin output edge detector count clock selection edge detector edge detector tipn0 pin (external event count input/ capture trigger input) tipn1 pin (capture trigger input) internal count clock 0 1 0 1 inttpnov signal inttpncc1 signal inttpncc0 signal remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 296 when the tpnce bit is set to 1, 16-bit timer/event counter p starts counting, and the output signals of the topn0 and topn1 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tpnccrm register, a compare match interrupt request sign al (inttpnccm) is generated, and the output signal of the topnm pin is inverted. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttpnov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tpnccrm register can be rewritten while the counter is oper ating. if it is rewritten, the new value is reflected at that time, and compared with the count value. figure 7-29. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 297 when the tpnce bit is set to 1, the 16- bit counter starts counting. when the valid edge input to the tipnm pin is detected, the count val ue of the 16-bit counter is stored in the tpn ccrm register, and a capture interrupt request signal (inttpnccm) is generated. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttpnov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 7-30. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 298 figure 7-31. register setting in free-running timer mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1 (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 101 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 1: free-running mode 0: operate with count clock selected by tpncks0 to tpncks2 bits 1: count on external event count input signal (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level with operation of topn0 pin disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level with operation of topn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 299 figure 7-31. register setting in free-running timer mode (2/2) (d) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of tipn0 pin input select valid edge of tipn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 (e) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (f) tmpn option register 0 (tpnopt0) 0 0 0/1 0/1 0 tpnopt0 overflow flag specifies if tpnccr0 register functions as capture or compare register specifies if tpnccr1 register functions as capture or compare register 0 0 0/1 tpnccs0 tpnovf tpnccs1 (g) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (h) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers function as captur e registers or compare registers depending on the setting of the tpnopt0.tpnccsm bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to the tipnm pin is detected. when the registers function as compare registers and when d m is set to the tpnccrm register, the inttpnccm signal is generated when the counter reaches (d m + 1), and the output signal of the topnm pin is inverted. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 300 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction set value changed cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> set value changed remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 301 figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnopt0 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 302 (b) when using capture/compare register as capture register figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 303 figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc1 register, tpnopt0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 304 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an in terval timer with the tpnccrm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttpnccm signal has been detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn pin output tpnccr1 register inttpncc1 signal topn1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding tpnccr m register must be re-set in the interrupt servicing that is executed when the inttpnccm signal is detected. the set value for re-setting the tpnccrm register c an be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 305 (b) pulse width measurement with capture register when pulse width measurement is performed with the tpnccrm register used as a capture register, software processing is necessary for reading the capt ure register each time the inttpnccm signal has been detected and for calculating an interval. ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pu lse width can be calculated by reading the value of the tpnccrm register in synchronization with the inttpnccm si gnal, and calculat ing the difference between the read value and the previously read value. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 306 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register tipn1 pin input tpnccr1 register inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tpnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 307 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> an overflow occurs. set the tpnovf0 and tpnovf 1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tpnccr0 register. read the tpnovf0 flag. if the tpnovf0 flag is 1, clear it to 0. because the tpnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0 (the tpnovf0 flag is cleared in <4>, and the tpnovf1 flag remains 1). because the tpnovf1 flag is 1, the puls e width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 308 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tpnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0. because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 309 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnov signal tpnovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tpnccrm register (setting of t he default value of the tipnm pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tpnccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 310 example when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnov signal tpnovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tpnccrm register (setting of t he default value of the tipnm pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tpnccrm register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 311 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tpnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tpnopt0 regist er. to accurately detect an overflow, read the tpnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tpnovf bit) overflow flag (tpnovf bit) l h l remark n = 0 to 3 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 312 7.5.7 pulse width measurement mode (tpnmd2 to tpnmd0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. each time the valid edge input to the tipnm pin has been detected, the count value of the 16-bit counter is stored in the tpnccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tpnccrm register after a capture interrupt request signal (inttpnccm) occurs. select either the tipn0 or tipn1 pin as the capture trigger input pin. specify ?no edge detected? by using the tpnioc1 register for the unused pins. when an external clock is used as the count clock, measur e the pulse width of the tipn1 pin because the external clock is fixed to the tipn0 pin. at this time, clear the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to 00 (capture trigger input (tipn0 pin): no edge detected). figure 7-34. configuration in pulse width measurement mode tpnccr0 register (capture) tpnce bit tpnccr1 register (capture) edge detector count clock selection edge detector edge detector tipn0 pin (external event count input/capture trigger input) tipn1 pin (capture trigger input) internal count clock clear inttpnov signal inttpncc0 signal inttpncc1 signal 16-bit counter remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 313 figure 7-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnccm signal inttpnov signal tpnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark n = 0 to 3 m = 0, 1 when the tpnce bit is set to 1, the 16- bit counter starts counting. when the valid edge input to the tipnm pin is later detected, the count value of the 16-bit counter is stored in the tpnccrm register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttpnccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tipnm pin even wh en the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttpnov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tpnopt0.t pnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tpnovf bit set (1) count + captured value) count clock cycle remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 314 figure 7-36. register setting in pu lse width measurement mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note setting is invalid when the tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 110 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tpnsye 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tpncks0 to tpncks2 bits 1: count external event count input signal (c) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of tipn0 pin input select valid edge of tipn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 315 figure 7-36. register setting in pu lse width measurement mode (2/2) (e) tmpn option register 0 (tpnopt0) 00000 tpnopt0 overflow flag 0 0 0/1 tpnccs0 tpnovf tpnccs1 (f) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (g) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers store the count va lue of the 16-bit counter when the valid edge input to the tipnm pin is detected. remarks 1. tmpn i/o control register 0 (tpnioc0) is not used in the pulse wid th measurement mode. 2. n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 316 (1) operation flow in pul se width measurement mode figure 7-37. software processing flow in pulse width measurement mode <1> <2> set tpnctl0 register (tpnce bit = 1) tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits), tpnctl1 register, tpnioc1 register, tpnioc2 register, tpnopt0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal d 0 0000h 0000h d 1 d 2 remark n = 0 to 3 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 317 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tpnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tpnopt0 regist er. to accurately detect an overflow, read the tpnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tpnovf bit) overflow flag (tpnovf bit) l h l remark n = 0 to 3 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 318 7.5.8 timer output operations the following table shows the operations and out put levels of the topn0 and topn1 pins. table 7-4. timer output control in each mode operation mode topn1 pin topn0 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? remark n = 0 to 3 table 7-5. truth table of topn0 and topn1 pins under control of timer output control bits tpnioc0.tpnolm bit tpnioc0.tpnoem bit tpnctl0.tpnce bit level of topnm pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 319 7.6 timer tuned operation function timer p and timer q have a timer tuned operation function. the timers that can be synchronized are listed in table 7-6. table 7-6. tuned operation mode of timers master timer slave timer tmp0 tmp1 ? tmp2 tmp3 tmq0 tmq1 tmq2 ? cautions 1. the tune d operation mode is enabled or disabled by the tpmctl1.tpmsye and tqnctl1.tqnsye bits. for tmp2, either or both tmp3 and tmq0 can be specified as slaves. 2. set the tuned operation mode using the following procedure. <1> set the tpmctl1.tpmsye and tqnctl1.tqnsye bits of the slave timer to enable the tuned operation. set the tpmctl1.tpmmd2 to tpmc tl1.tpmmd0 and tqnctl1.tpnmd2 to tqnctl1.tpnmd0 bits of the slave timer to the free-running mode. <2> set the timer mode by using the tpnctl1.tpnmd2 to tpnctl1.tpnmd0 and tqnctl1.tpnmd2 to tqnctl1.tpnmd0 bits. at this time, do not set the tpnctl1.tpn sye and tqnctl1.tqnsye bits of the master timer. <3> set the compare register value of the master and slave timers. <4> set the tpmctl0.tpmce and tqnctl0.tqnc e bits of the sla ve timer to enable operation on the internal operating clock. <5> set the tpnctl0.tpnce a nd tqnctl0.tqnce bits of th e master timer to enable operation on the internal operating clock. remark m = 1, 3, n = 0, 2 tables 7-7 and 7-8 show the timer modes that can be used in the tuned operation mode ( : settable, : not settable). table 7-7. timer modes usable in tuned operation mode master timer free-running mode pwm mode triangular wave pwm mode tmp0 tmp2 tmq1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 320 table 7-8. timer output functions free-running mode pwm mode triangular wave pwm mode tuned channel timer pin tuning off tuning on tuning off tuning on tuning off tuning on top00 ppg toggle n/a tmp0 (master) top01 ppg pwm n/a top10 pgp toggle pwm n/a ch0 tmp1 (slave) top11 ppg pwm n/a top20 ppg toggle pwm n/a tmp2 (master) top21 ppg pwm n/a top30 ppg toggle pwm n/a tmp3 (slave) top31 ppg pwm n/a toq00 ppg toggle pwm toggle n/a ch1 tmq0 (slave) toq01 to toq03 ppg pwm triangular wave pwm n/a toq10 ppg toggle toggle tmq1 (master) toq11 to toq13 ppg pwm triangular wave pwm toq20 ppg toggle pwm toggle triangular wave pwm ch2 tmq2 (slave) toq21 to toq23 ppg pwm triangular wave pwm remark the timing of transmitting data from t he compare register of the master timer to the compare register of the slave timer is as follows. ppg: cpu write timing toggle, pwm, triangular wave pwm: timing at which timer counter and compare register match topn0 and toqm0 (n = 0 to 3, m = 0 to 2) chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 321 figure 7-38. tuned operation image (tmp2, tmp3, tmq0) tmp2 tmp2 (master) + tmp3 (slave) + tmq0 (slave) top21 (pwm output) 16-bit timer/counter unit operation tuned operation five pwm outputs are available when pwm is operated as a single unit. 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare tmp3 top31 (pwm output) tmq0 toq01 (pwm output) toq02 (pwm output) toq03 (pwm output) top21 (pwm output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top30 (pwm output) 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top31 (pwm output) toq01 (pwm output) toq00 (pwm output) toq02 (pwm output) toq03 (pwm output) seven pwm outputs are available when pwm is operated in tuned operation mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 322 figure 7-39. basic operation timing of tuned pwm function (tmp2, tmp3, tmq0) top20 top21 top30 toq00 toq01 toq02 toq03 top31 tp2ccr0 tp2ce inttp2cc0 match interrupt inttp2cc1 match interrupt inttp3cc0 match interrupt inttp3cc1 match interrupt inttq0cc0 match interrupt inttq0cc1 match interrupt inttq0cc2 match interrupt inttq0cc3 match interrupt tp3ce tq0ce ffffh 0000h tmp2 16-bit counter d 00 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 tp2ccr1 d 10 tp3ccr0 d 20 tp3ccr1 d 30 tq0ccr0 d 40 tq0ccr1 d 50 tq0ccr2 d 60 tq0ccr3 d 70 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 323 7.7 selector function in the v850es/hj2, the alternate-func tion pins of port and peripheral i/o (t mp, tmm0, or uarta) can be used to select the capture trigger input of tmp. by using this function, the following is possible. ? the tip10 and tip11 input signals of tmp1 can be sele cted from the port/timer alte rnate-function pins (tip10 and tip11 pins) and the uarta reception alternate-function pins (rxda0 and rxda1). the tip31 input signal of tmp3 can be selected from a port/timer alternate-fu nction pin (tip31 pin) and the uarta re ception alternate- function pin (rxda3). when the rxda0, rxda1, or rxda3 signal of uarta0, uarta1, or uarta3 is selected, the baud rate error of the uarta lin reception transfer can be calculated. ? the tip01 input signal of tmp0 can be selected from the port/timer alternate-function pin (tip01 pin) and the inttm0eq0 signal of tmm0. cautions 1. when using the selector function, set the capture trigger input of tmp before connecting the timer. 2. when setting the selector function, first disable the peripheral i/o to be connected (tmp, tmm0, or uarta). the capture input for the selector functi on is specified by the following register. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 324 (1) selector operation control register 0 (selcnt0) the selcnt0 register is an 8-bit register that se lects the capture trigger for tmp0, tmp1, and tmp3. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tip31 pin input rxda3 pin input isel06 note 1 0 1 selection of tip31 input signal (tmp3) selcnt0 isel06 isel05 isel04 isel03 isel02 0 0 tip11 pin input rxda1 pin input isel04 0 1 selection of tip11 input signal (tmp1) tip10 pin input rxda0 pin input isel03 0 1 selection of tip10 input signal (tmp1) tip01 pin input inttm0eq0 interrupt of tmm0 isel02 note 2 0 1 selection of tip01 input signal (tmp0) tip30 pin input rxda2 pin input isel05 0 1 selection of tip30 input signal (tmp3) after reset: 00h r/w address: fffff308h notes 1. the pd70f3709 and 70f3710 do not have the rxda3 pin. fix the isel06 bit of these products to 0. 2. use the inttm0eq0 interrupt signal as the tip01 input signal under the following condition. tmm operation clock tmp operation clock 4 caution to set the isel02 to isel06 bits to 1, set the corresponding pin in the capture input mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17717ej2v0ud 325 7.8 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tpnccr0 and tpnccr1 registers if the capture trigger is input immediately after the tpnce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0001h 0000h tipn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tpnce bit tpnccr0 register tipn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input preliminary user?s manual u17717ej2v0ud 326 chapter 8 16-bit timer/event counter q (tmq) timer q (tmq) is a 16-bit timer/event counter. the v850es/hj2 incorpor ates tmq0 to tmq2. 8.1 overview an outline of tmqn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 4 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 4 ? capture/compare match interrupt request signals: 4 ? timer output pins: 4 remark n = 0 to 2 8.2 functions tmqn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? triangular wave pwm output ? timer tuned operation function remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 327 8.3 configuration tmq0 to tmq2 include the following hardware. table 8-1. configuration of tmq0 to tmq2 item configuration timer register 16-bit counter registers tmqn capture/compare registers 0 to 3 (tqnccr0 to tqnccr3) tmqn counter read buffer register (tqncnt) ccr0 to ccr3 buffer registers timer inputs 4 (tiqn0 note 1 to tiqn3 pins) timer outputs 4 (toqn0 to toqn3 pins) control registers note 2 tmqn control registers 0, 1 (tqnctl0, tqnctl1) tmqn i/o control registers 0 to 2 (tqnioc0 to tqnioc2) tmqn option register 0 (tqnopt0) notes 1. the tiqn0 pin functions alternately as a capt ure trigger input signal, external event count input signal, and external trigger input signal. 2. when using the functions of the tiqn0 to tiqn3 and toqn0 to toqn3 pins, see table 4-25 using port pin as alternate-function pin . figure 8-1. block diagram of tmq0 to tmq2 tqncnt tqnccr0 tqnccr1 tqnccr2 toqn0 inttqnov ccr2 buffer register tqnccr3 ccr3 buffer register toqn1 toqn2 toqn3 inttqncc0 inttqncc1 inttqncc2 inttqncc3 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiqn0 tiqn1 tiqn2 tiqn3 selector internal bus internal bus selector edge detector ccr0 buffer register ccr1 buffer register 16-bit counter output controller clear remarks 1. f xx : main clock frequency 2. n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 328 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tqncnt register. when the tqnctl0.tqnce bit = 0, the va lue of the 16-bit counter is ffffh. if the tqncnt register is read at this time, 0000h is read. reset sets the tqnce bit to 0. therefor e, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tqnccr0 register is used as a compare regist er, the value written to the tqnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttqncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tqnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tqnccr1 register is used as a compare regist er, the value written to the tqnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttqncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tqnccr1 register is cleared to 0000h. (4) ccr2 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tqnccr2 register is used as a compare regist er, the value written to the tqnccr2 register is transferred to the ccr2 buffer register. when the count value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttqncc2) is generated. the ccr2 buffer register cannot be read or written directly. the ccr2 buffer register is cleared to 0000h after reset, as the tqnccr2 register is cleared to 0000h. (5) ccr3 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tqnccr3 register is used as a compare regist er, the value written to the tqnccr3 register is transferred to the ccr3 buffer register. when the count value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttqncc3) is generated. the ccr3 buffer register cannot be read or written directly. the ccr3 buffer register is cleared to 0000h after reset, as the tqnccr3 register is cleared to 0000h. (6) edge detector this circuit detects the valid edges input to the tiq n0 and tiqn3 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tqnioc1 and tqnioc2 registers. (7) output controller this circuit controls the output of the toqn0 to t oqn3 pins. the output contro ller is controlled by the tqnioc0 register. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 329 (8) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 330 8.4 registers the registers that control tmqn are as follows. ? tmqn control register 0 (tqnctl0) ? tmqn control register 1 (tqnctl1) ? tmqn i/o control register 0 (tqnioc0) ? tmqn i/o control register 1 (tqnioc1) ? tmqn i/o control register 2 (tqnioc2) ? tmqn option register 0 (tqnopt0) ? tmqn capture/compare register 0 (tqnccr0) ? tmqn capture/compare register 1 (tqnccr1) ? tmqn capture/compare register 2 (tqnccr2) ? tmqn capture/compare register 3 (tqnccr3) ? tmqn counter read buffer register (tqncnt) remark when using the functions of the tiqn0 to tiqn3 and toqn0 to toqn3 pins, see table 4-25 using port pin as alternate-function pin . chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 331 (1) tmqn control register 0 (tqnctl0) the tqnctl0 register is an 8-bit register that controls the operation of tmqn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tqnctl0 register by software. tqnce tmqn operation disabled (tmqn reset asynchronously note ). tmqn operation enabled. tmqn operation started. tqnce 0 1 tmqn operation control tqnctl0 (n = 0 to 2) 0 0 0 0 tqncks2 tqncks1 tqncks0 654321 after reset: 00h r/w address: tq0ctl0 fffff540h, tq1ctl0 fffff610h, tq2ctl0 fffff620h 7 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tqncks2 0 0 0 0 1 1 1 1 internal count clock selection tqncks1 0 0 1 1 0 0 1 1 tqncks0 0 1 0 1 0 1 0 1 note tqnopt0.tqnovf bit, 16-bit counter, timer output (toqn0 to toqn3 pins) cautions 1. set the tqncks2 to tqncks0 bits when the tqnce bit = 0. when the value of the tqnce bit is changed from 0 to 1, the tqncks2 to tqncks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 332 (2) tmqn control register 1 (tqnctl1) the tqnctl1 register is an 8-bit register that controls the operation of tmqn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) tqnsye tqnest 0 1 software trigger control tqnctl1 (n = 0 to 2) tqnest tqneee 0 0 tqnmd2 tqnmd1 tqnmd0 654321 after reset: 00h r/w address: tq0ctl1 fffff541h, tq1ctl1 fffff611h, tq2ctl1 fffff621h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tqnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tqnest bit as the trigger. 7 0 ? slave timer tqnsye 0 1 tuned operation mode enable control tuned operation mode (specification of slave operation) in this mode, timer p can operate in synchronization with a master timer. independent operation mode (asynchronous operation mode) for the tuned operation mode, see 8.6 timer tuned operation function . master timer tmp2 tmq1 tmp3 tmq2 tmq0 ? cautions 1. the tqnest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. be sure to clear bits 3 and 4 to ?0?. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 333 (2/2) disable operation with external event count input. (perform counting with the count clock selected by the tqnctl0.tqnck0 to tqnck2 bits.) tqneee 0 1 count clock selection the tqneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode triangular wave pwm mode tqnmd2 0 0 0 0 1 1 1 1 timer mode selection tqnmd1 0 0 1 1 0 0 1 1 tqnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) cautions 1. external event count input is selected in the external event count mode regardless of the value of the tqneee bit. 2. set the tqneee and tqnmd2 to tqnmd0 bits when the tqnctl0.tqnce bit = 0. (the same value can be written when the tqnce bit = 1.) the operation is not guaranteed when rewr iting is performed with the tqnce bit = 1. if rewriting was mistakenly performed, clear the tqnce bit to 0 and then set the bits again. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 334 (3) tmqn i/o control register 0 (tqnioc0) the tqnioc0 register is an 8-bit register that controls the timer output (toqn0 to toqn3 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tqnol3 tqnolm 0 1 toqnm pin output level setting (m = 0 to 3) toqnm pin output inversion disabled toqnm pin output inversion enabled tqnioc0 (n = 0 to 2) tqnoe3 tqnol2 tqnoe2 tqnol1 tqnoe1 tqnol0 tqnoe0 654321 after reset: 00h r/w address: tq0ioc0 fffff542h, tq1ioc0 fffff612h, tq2ioc0 fffff622h tqnoem 0 1 toqnm pin output setting (m = 0 to 3) timer output disabled ? when tqnolm bit = 0: low level is output from the toqnm pin ? when tqnolm bit = 1: high level is output from the toqnm pin 7 0 timer output enabled (a square wave is output from the toqnm pin). cautions 1. rewrite the tqnolm and tqnoem bits when the tqnctl0.tqnce bit = 0. (the same value can be written when the tqnce bit = 1.) if rewriting was mistakenly performed, clear the tqnce bit to 0 and then set the bits again. 2. even if the tqnolm bit is manipulated when the tqnce and tqnoem bits are 0, the toqnm pin output level varies. remark m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 335 (4) tmqn i/o control register 1 (tqnioc1) the tqnioc1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (tiqn0 to tiqn3 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tqnis7 tqnis7 0 0 1 1 tqnis6 0 1 0 1 capture trigger input signal (tiqn3 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tqnioc1 (n = 0 to 2) tqnis6 tqnis5 tqnis4 tqnis3 tqnis2 tqnis1 tqnis0 654321 after reset: 00h r/w address: tq0ioc1 fffff543h, tq1ioc1 fffff613h, tq2ioc1 fffff623h tqnis5 0 0 1 1 tqnis4 0 1 0 1 capture trigger input signal (tiqn2 pin) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tqnis3 0 0 1 1 tqnis2 0 1 0 1 capture trigger input signal (tiqn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tqnis1 0 0 1 1 tqnis0 0 1 0 1 capture trigger input signal (tiqn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges cautions 1. rewrite the tqnis7 to tqnis0 bits when the tqnctl0.tqnce bit = 0. (the same value can be written when the tqnce bit = 1.) if rewriting was mistakenly performed, clear the tqnce bit to 0 and then set the bits again. 2. the tqnis7 to tqnis0 bits are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 336 (5) tmqn i/o control register 2 (tqnioc2) the tqnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tiqn0 pin) and external trigger input signal (tiqn0 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tqnees1 0 0 1 1 tqnees0 0 1 0 1 external event count input signal (tiqn0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tqnioc2 (n = 0 to 2) 0 0 0 tqnees1 tqnees0 tqnets1 tqnets0 654321 after reset: 00h r/w address: tq0ioc2 fffff544h, tq1ioc2 fffff614h, tq2ioc2 fffff624h tqnets1 0 0 1 1 tqnets0 0 1 0 1 external trigger input signal (tiqn0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tqnees1 , tqnees0, tqnets1, and tqnets0 bits when the tqnctl0.tqnce bit = 0. (the same value can be written when the tqnce bit = 1.) if rewriting was mistakenly performed, clear the tqnce bit to 0 and then set the bits again. 2. the tqnees1 and tqnees0 bi ts are valid only when the tqnctl1.tqneee bit = 1 or when the external event count mode (tqnctl1.tqn md2 to tqnctl1.tqnmd0 bits = 001) has been set. 3. the tqnets1 and tqnets0 bits are valid only when the external trigger pulse output mode (tqnctl1.tqnmd2 to tqnctl1.tqnmd0 bits = 010) or the one-shot pulse output mode (tqnctl1.tqnmd2 to tqnctl1.tqnmd0 = 011) is set. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 337 (6) tmqn option register 0 (tqnopt0) the tqnopt0 register is an 8-bit register used to set the capture/co mpare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tqnccs3 tqnccsm 0 1 tqnccrm register capture/compare selection the tqnccsm bit setting is valid only in the free-running timer mode. compare register selected capture register selected tqnopt0 (n = 0 to 2) tqnccs2 tqnccs1 tqnccs0 0 0 0 tqnovf 654321 after reset: 00h r/w address: tq0opt0 fffff545h, tq1opt0 fffff615h, tq2opt0 fffff625h tqnovf set (1) reset (0) tmqn overflow detection the tqnovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. an interrupt request signal (inttqnov) is generated at the same time that the tqnovf bit is set to 1. the inttqnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. the tqnovf bit is not cleared even when the tqnovf bit or the tqnopt0 register are read when the tqnovf bit = 1. the tqnovf bit can be both read and written, but the tqnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmqn. overflow occurred tqnovf bit 0 written or tqnctl0.tqnce bit = 0 7 0 cautions 1. rewrite the tqnccs 3 to tqnccs0 bits when the tqnctl0.tqnce bit = 0. (the same value can be written when the tqnce bit = 1.) if rewriting was mistakenly performed, clear the tqnce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3 to ?0?. remark m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 338 (7) tmqn capture/compare register 0 (tqnccr0) the tqnccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tqno pt0.tqnccs0 bit. in the pulse width measurement mode, the tqnccr0 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tqnccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tqnccr0 register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tqnccr0 (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r/w address: tq0ccr0 fffff546h, tq1ccr0 fffff616h, tq2ccr0 fffff626h 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 339 (a) function as compare register the tqnccr0 register can be rewritten even when the tqnctl0.tqnce bit = 1. the set value of the tqnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttqncc0) is generated. if toqn0 pin output is enab led at this time, the out put of the toqn0 pin is inverted. when the tqnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, pwm output mode, or triangular wave pwm mode, the value of the 16-bit counter is clea red (0000h) if its count va lue matches the value of the ccr0 buffer register. (b) function as capture register when the tqnccr0 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tqnccr0 register if the valid ed ge of the capture trigger input pin (tiqn0 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tqnccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiqn0 pin) is detected. even if the capture operation and reading the tqnc cr0 register conflict, the correct value of the tqnccr0 register can be read. remark n = 0 to 2 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 340 (8) tmqn capture/compare register 1 (tqnccr1) the tqnccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tqno pt0.tqnccs1 bit. in the pulse width measurement mode, the tqnccr1 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tqnccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tqnccr1 register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tqnccr1 (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r/w address: tq0ccr1 fffff548h, tq1ccr1 fffff618h, tq2ccr1 fffff628h 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 341 (a) function as compare register the tqnccr1 register can be rewritten even when the tqnctl0.tqnce bit = 1. the set value of the tqnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttqncc1) is generated. if toqn1 pin output is e nabled at this time, the output of the toqn1 pin is inverted. (b) function as capture register when the tqnccr1 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tqnccr1 register if the valid ed ge of the capture trigger input pin (tiqn1 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tqnccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiqn1 pin) is detected. even if the capture operation and reading the tqnc cr1 register conflict, the correct value of the tqnccr1 register can be read. remark n = 0 to 2 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 342 (9) tmqn capture/compare register 2 (tqnccr2) the tqnccr2 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tqno pt0.tqnccs2 bit. in the pulse width measurement mode, the tqnccr2 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tqnccr2 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tqnccr2 register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tqnccr2 (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r/w address: tq0ccr2 fffff54ah, tq1ccr2 fffff61ah, tq2ccr2 fffff62ah 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 343 (a) function as compare register the tqnccr2 register can be rewritten even when the tqnctl0.tqnce bit = 1. the set value of the tqnccr2 register is transferred to the ccr2 buffer register. when the value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttqncc2) is generated. if toqn2 pin output is e nabled at this time, the output of the toqn2 pin is inverted. (b) function as capture register when the tqnccr2 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tqnccr2 register if the valid ed ge of the capture trigger input pin (tiqn2 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tqnccr2 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiqn2 pin) is detected. even if the capture operation and reading the tqnc cr2 register conflict, the correct value of the tqnccr2 register can be read. remark n = 0 to 2 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 344 (10) tmqn capture/compare register 3 (tqnccr3) the tqnccr3 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tqno pt0.tqnccs3 bit. in the pulse width measurement mode, the tqnccr3 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tqnccr3 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tqnccr3 register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tqnccr3 (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r/w address: tq0ccr3 fffff54ch, tq1ccr3 fffff61ch, tq2ccr3 fffff62ch 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 345 (a) function as compare register the tqnccr3 register can be rewritten even when the tqnctl0.tqnce bit = 1. the set value of the tqnccr3 register is transferred to the ccr3 buffer register. when the value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttqncc3) is generated. if toqn3 pin output is e nabled at this time, the output of the toqn3 pin is inverted. (b) function as capture register when the tqnccr3 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tqnccr3 register if the valid ed ge of the capture trigger input pin (tiqn3 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tqnccr3 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiqn3 pin) is detected. even if the capture operation and reading the tqnc cr3 register conflict, the correct value of the tqnccr3 register can be read. remark n = 0 to 2 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 346 (11) tmqn counter read buffer register (tqncnt) the tqncnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tqnctl0.tqnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tqncnt register is cleared to 0000h wh en the tqnce bit = 0. if the tqncnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tqncnt register is cleared to 000 0h after reset, as the tqnce bit is cleared to 0. caution accessing the tqncnt regist er is prohibited in the followi ng statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tqncnt (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r address: tq0cnt fffff54eh, tq1cnt fffff61eh, tq2cnt fffff62eh 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 347 (12) tiqnm pin noise eliminatio n control register (qnmnfc) the qnmnfc register is an 8-bit regist er that sets the digital noise filter of the timer q input pin for noise elimination. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: q00nfc: fffffb50h (tiq00 pin) q01nfc: fffffb54h (tiq01 pin) q02nfc: fffffb58h (tiq02 pin) q03nfc: fffffb5ch (tiq03 pin) q10nfc: fffffb60h (tiq10 pin) q11nfc: fffffb64h (tiq11 pin) q12nfc: fffffb68h (tiq12 pin) q13nfc: fffffb6ch (tiq13 pin) q20nfc: fffffb70h (tiq20 pin) q21nfc: fffffb74h (tiq21 pin) q22nfc: fffffb78h (tiq22 pin) q23nfc: fffffb7ch (tiq23 pin) 7 6 5 4 3 2 1 0 qnmnfc 0 nfsts 0 0 0 nfc2 nfc1 nfc0 (n = 0 to 2, m = 0 to 3) nfsts setting of number of times of sampling by digital noise filter 0 3 times 1 2 times nfc2 nfc1 nfc0 sampling clock 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /16 1 0 0 f xx /32 1 0 1 f xx /64 other than above setting prohibited cautions 1. be sure to clea r bits 3 to 5 and 7 to ?0?. 2. a signal input to the timer i nput pin (tiqnm) before the qnmnfc register is set is output wi th digital noise eliminated. therefore, set the sampling clock (nfc2 to nfc0) and the number of times of sampling (nfsts) by using the qnmnfc register, wait for initialization time = (sampling clock) (number of times of sampling), and enable the timer operation. remark the width of the noise that can be accu rately eliminated is (sampling clock) (number of times of sampling ? 1). even noise with a width narrower than this may cause a miscount if it is synchronized with the sampling clock. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 348 8.5 operation tmqn can perform the following operations. operation tqnctl1.tqnest bit (software trigger bit) tiqn0 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable triangular wave pwm mode invalid invalid compare only batch write notes 1. to use the external event count m ode, specify that the valid edge of the tiqn0 pin capture trigger input is not detected (by clearing the tqnioc1.tq nis1 and tqnioc1.tqnis0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by cleari ng the tqnctl1.tqneee bit to 0). remark n= 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 349 8.5.1 interval timer mode (t qnmd2 to tqnmd0 bits = 000) in the interval timer mode, an interrupt request signal (inttqncc0) is generated at t he specified interval if the tqnctl0.tqnce bit is set to 1. a square wave whose hal f cycle is equal to the interval can be output from the toqn0 pin. usually, the tqnccr1 to tqnccr3 registers are not used in the interval timer mode. figure 8-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tqnce bit tqnccr0 register count clock selection clear match signal toqn0 pin inttqncc0 signal remark n = 0 to 2 figure 8-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tqnce bit tqnccr0 register toqn0 pin output inttqncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 350 when the tqnce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and the counter starts counting. at this time, the output of the toqn0 pin is inverted. additionally, the set value of the tqnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, the output of the toqn0 pin is in verted, and a compare match interrupt request signal (inttqncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tqnccr0 register + 1) count clock cycle figure 8-4. register setting for in terval timer mode operation (1/2) (a) tmqn control register 0 (tqnctl0) 0/1 0 0 0 0 tqnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tqncks2 tqncks1 tqncks0 tqnce (b) tmqn control register 1 (tqnctl1) 0 0 0/1 note 00 tqnctl1 0, 0, 0: interval timer mode 000 tqnmd2 tqnmd1 tqnmd0 tqneee tqnest tqnsye 0: operate on count clock selected by bits tqncks0 to tqncks2 1: count with external event count input signal note this bit can be set to 1 only when the interrupt request signals (inttqncc0 and inttqncck) are masked by the interrupt mask flags (tqnccmk0 to tqnccmkk) and the timer output (toqnk) is performed at the same time. however, the tqnccr0 and tqnccrk registers must be set to the same value (see 8.5.1 (2) (d) operation of tqnccr1 to tqnccr3 registers ) (k = 1 to 3). remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 351 figure 8-4. register setting for in terval timer mode operation (2/2) (c) tmqn i/o control register 0 (tqnioc0) 0/1 0/1 0/1 0/1 0/1 tqnioc0 0: disable toqn0 pin output 1: enable toqn0 pin output setting of output level with operation of toqn0 pin disabled 0: low level 1: high level 0: disable toqn1 pin output 1: enable toqn1 pin output setting of output level with operation of toqn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tqnoe1 tqnol0 tqnoe0 tqnol1 0: disable toqn2 pin output 1: enable toqn2 pin output setting of output level with operation of toqn2 pin disabled 0: low level 1: high level 0: disable toqn3 pin output 1: enable toqn3 pin output setting of output level with operation of toqn3 pin disabled 0: low level 1: high level tqnoe3 tqnol2 tqnoe2 tqnol3 (d) tmqn counter read buffer register (tqncnt) by reading the tqncnt register, the count va lue of the 16-bit counter can be read. (e) tmqn capture/compare register 0 (tqnccr0) if the tqnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmqn capture/compare register s 1 to 3 (tqnccr1 to tqnccr3) usually, the tqnccr1 to tqnccr3 registers are not us ed in the interval timer mode. however, the set value of the tqnccr1 to tqnccr3 registers are trans ferred to the ccr1 to ccr3 buffer registers. the compare match interrupt request signals (inttqn ccr1 to inttqnccr3) is generated when the count value of the 16-bit counter matches the va lue of the ccr1 to ccr3 buffer registers. therefore, mask the interrupt request by using the corresponding interrupt mask flags (tqnccmk1 to tqnccmk3). remarks 1. tmqn i/o control register 1 (tqnioc1), tmqn i/o control register 2 (tqnioc2), and tmqn option register 0 (tqnopt0) are not used in the interval timer mode. 2. n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 352 (1) interval timer mode operation flow figure 8-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tqnce bit tqnccr0 register toqn0 pin output inttqncc0 signal d 0 d 0 d 0 d 0 <1> <2> tqnce bit = 1 tqnce bit = 0 register initial setting tqnctl0 register (tqncks0 to tqncks2 bits) tqnctl1 register, tqnioc0 register, tqnccr0 register initial setting of these registers is performed before setting the tqnce bit to 1. the tqncks0 to tqncks2 bits can be set at the same time when counting has been started (tqnce bit = 1). the counter is initialized and counting is stopped by clearing the tqnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 353 (2) interval timer mode operation timing (a) operation if tqnccr0 re gister is set to 0000h if the tqnccr0 register is set to 0000h, the inttq ncc0 signal is generated at each count clock subsequent to the first count clock, and t he output of the toqn0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tqnce bit tqnccr0 register toqn0 pin output inttqncc0 signal 0000h interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0 to 2 (b) operation if tqnccr0 register is set to ffffh if the tqnccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing. the inttqncc0 signal is generated and the output of the toqn0 pin is inverted. at this time, an overflow interrupt request signal (inttqnov) is not generated, nor is the overflow flag (tqnopt0.tqnovf bit) set to 1. ffffh 16-bit counter 0000h tqnce bit tqnccr0 register toqn0 pin output inttqncc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 354 (c) notes on rewriting tqnccr0 register to change the value of the tqnccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tqnccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tqnce bit tqnccr0 register tqnol0 bit toqn0 pin output inttqncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0 to 2 if the value of the tqnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tqnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttqncc0 signal is generated and the output of the toqn0 pin is inverted. therefore, the inttqncc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 355 (d) operation of tqnccr1 to tqnccr3 registers figure 8-6. configuration of tqnccr1 to tqnccr3 registers ccr0 buffer register tqnce bit tqnccr0 register clear match signal inttqncc0 signal toqn3 pin inttqncc3 signal toqn0 pin tqnccr1 register ccr1 buffer register match signal toqn1 pin inttqncc1 signal tqnccr3 register ccr3 buffer register match signal toqn2 pin inttqncc2 signal tqnccr2 register ccr2 buffer register match signal output controller count clock selection output controller output controller output controller 16-bit counter remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 356 if the set value of the tqnccrk register is less than the set value of the tqnccr0 register, the inttqncck signal is generated once per cycle. at t he same time, the output of the topqnk pin is inverted. the toqnk pin outputs a square wave with the sa me cycle as that output by the toqn0 pin. remark k = 1 to 3, n = 0 to 2 figure 8-7. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register toqn0 pin output inttqncc0 signal tqnccr1 register toqn1 pin output inttqncc1 signal tqnccr2 register toqn2 pin output inttqncc2 signal tqnccr3 register toqn3 pin output inttqncc3 signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 357 if the set value of the tqnccrk regi ster is greater than the set value of the tqnccr0 register, the count value of the 16-bit counter does not match the value of the tqnccr k register. consequently, the inttqncck signal is not generated, nor is the output of the toqnk pin changed. remark k = 1 to 3, n = 0 to 2 figure 8-8. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register toqn0 pin output inttqncc0 signal tqnccr1 register toqn1 pin output inttqncc1 signal tqnccr2 register toqn2 pin output inttqncc2 signal tqnccr3 register toqn3 pin output inttqncc3 signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 358 8.5.2 external event count mode (tqnmd2 to tqnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tqnctl0.tqnce bit is set to 1, and an interrupt request signal (inttqncc0) is generated each time the specified number of edges have been counted. the toqn0 pin cannot be used. usually, the tqnccr1 to tqnccr3 registers are not used in the external event count mode. figure 8-9. configuration in external event count mode 16-bit counter ccr0 buffer register tqnce bit tqnccr0 register edge detector clear match signal inttqncc0 signal tiqn0 pin (external event count input) remark n = 0 to 2 figure 8-10. basic timing in external event count mode ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal d 0 d 0 d 0 d 0 16-bit counter tqnccr0 register nttqncc0 signal external event count input (tiqn0 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remarks 1. this figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input. 2. n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 359 when the tqnce bit is set to 1, the value of the 16-bit count er is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detec ted. additionally, the set value of the tqnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttqncc0) is generated. the inttqncc0 signal is generated each time the valid edge of the external event co unt input has been detected (set value of tqnccr0 register + 1) times. figure 8-11. register setting for operati on in external event count mode (1/2) (a) tmqn control register 0 (tqnctl0) 0/1 0 0 0 0 tqnctl0 0: stop counting 1: enable counting 000 tqncks2 tqncks1 tqncks0 tqnce (b) tmqn control register 1 (tqnctl1) 00000 tqnctl1 0, 0, 1: external event count mode 001 tqnmd2 tqnmd1 tqnmd0 tqneee tqnest tqnsye (c) tmqn i/o control register 0 (tqnioc0) 00000 tqnioc0 0: disable toqn0 pin output 0: disable toqn1 pin output 000 tqnoe1 tqnol0 tqnoe0 tqnol1 tqnoe3 tqnol2 tqnoe2 tqnol3 0: disable toqn2 pin output 0: disable toqn3 pin output (d) tmqn i/o control register 2 (tqnioc2) 0 0 0 0 0/1 tqnioc2 select valid edge of external event count input 0/1 0 0 tqnees0 tqnets1 tqnets0 tqnees1 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 360 figure 8-11. register setting for operati on in external event count mode (2/2) (e) tmqn counter read buffer register (tqncnt) the count value of the 16-bit counter can be read by reading the tqncnt register. (f) tmqn capture/compare register 0 (tqnccr0) if d 0 is set to the tqnccr0 regist er, the counter is cleared and a compare match interrupt request signal (inttqncc0) is generated when the nu mber of external event counts reaches (d 0 + 1). (g) tmqn capture/compare regist ers 1 to 3 (tqnccr1 to tqnccr3) usually, the tqnccr1 to tqnccr3 registers are not us ed in the external event count mode. however, the set value of the tqnccr1 to tqnccr3 regist ers are transferred to the ccr1 to ccr3 buffer registers. when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers, compare match interrupt request si gnals (inttqncc1 to inttqncc3) are generated. therefore, mask the interrupt signal by using t he interrupt mask flags (t qnccmk1 to tqnccmk3). remarks 1. the tmqn i/o control register 1 (tqnioc1) and tmqn option register 0 (tqnopt0) are not used in the external event count mode. 2. n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 361 (1) external event count mode operation flow figure 8-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal d 0 d 0 d 0 d 0 <1> <2> tqnce bit = 1 tqnce bit = 0 register initial setting tqnctl0 register (tqncks0 to tqncks2 bits) tqnctl1 register, tqnioc0 register, tqnioc2 register, tqnccr0 register initial setting of these registers is performed before setting the tqnce bit to 1. the tqncks0 to tqncks2 bits can be set at the same time when counting has been started (tqnce bit = 1). the counter is initialized and counting is stopped by clearing the tqnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 362 (2) operation timing in external event count mode cautions 1. in the external event count m ode, do not set the tqnccr0 register to 0000h. 2. in the external e vent count mode, use of the timer output is disabled. if performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (tqnctl1.tqnmd2 to tqnctl1.tqnmd0 bits = 000, tqnctl1.tqneee bit = 1). (a) operation if tqnccr0 register is set to ffffh if the tqnccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the in ttqncc0 signal is generated. at this time, the tqnopt0.tqnovf bit is not set. ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 363 (b) notes on rewriting the tqnccr0 register to change the value of the tqnccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tqnccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) remark n = 0 to 2 if the value of the tqnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tqnccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttqncc0 signal is generated. therefore, the inttqncc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 364 (c) operation of tqnccr1 to tqnccr3 registers figure 8-13. configuration of tqnccr1 to tqnccr3 registers ccr0 buffer register tqnce bit tqnccr0 register clear match signal inttqncc0 signal inttqncc3 signal tiqn0 pin tqnccr1 register ccr1 buffer register match signal inttqncc1 signal tqnccr3 register ccr3 buffer register match signal inttqncc2 signal tqnccr2 register ccr2 buffer register match signal 16-bit counter edge detector remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 365 if the set value of the tqnccrk register is smalle r than the set value of the tqnccr0 register, the inttqncck signal is generated once per cycle. remark k = 1 to 3, n = 0 to 2 figure 8-14. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal tqnccr1 register inttqncc1 signal tqnccr2 register inttqncc2 signal tqnccr3 register inttqncc3 signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 366 if the set value of the tqnccrk regi ster is greater than the set va lue of the tqnccr0 register, the inttqncck signal is not generated because the count va lue of the 16-bit counter and the value of the tqnccrk register do not match. remark k = 1 to 3, n = 0 to 2 figure 8-15. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal tqnccr1 register inttqncc1 signal tqnccr2 register inttqncc2 signal tqnccr3 register inttqncc3 signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 367 8.5.3 external trigger pulse output m ode (tqnmd2 to tq nmd0 bits = 010) in the external trigger pulse output mode, 16-bit ti mer/event counter q waits for a trigger when the tqnctl0.tqnce bit is set to 1. when the valid edge of an external trigger input signal is detected, 16-bit timer/event counter q starts counting, and outputs a pwm waveform from the toqn1 to toqn3 pins. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the toqn0 pin. figure 8-16. configuration in external trigger pulse output mode ccr0 buffer register tqnce bit tqnccr0 register clear match signal inttqncc0 signal toqn3 pin inttqncc3 signal toqn0 pin tiqn0 pin transfer s r tqnccr1 register ccr1 buffer register match signal toqn1 pin inttqncc1 signal transfer transfer s r tqnccr3 register ccr3 buffer register match signal transfer toqn2 pin inttqncc2 signal s r tqnccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller output controller (rs-ff) output controller remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 368 figure 8-17. basic timing in exte rnal trigger pulse output mode d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 1 d 2 d 3 active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 3 ) active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) wait for trigger active level width (d 3 ) cycle (d 0 + 1) ffffh 16-bit counter 0000h tqnce bit external trigger input (tiqn0 pin input) tqnccr0 register inttqncc0 signal toqn0 pin output (only when software trigger is used) tqnccr1 register inttqncc1 signal toqn1 pin output tqnccr2 register inttqncc2 signal toqn2 pin output tqnccr3 register inttqncc3 signal toqn3 pin output active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) d 0 d 1 d 3 d 2 d 0 d 0 d 0 d 0 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 369 16-bit timer/event counter q waits for a trigger when the tqnce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the toqnk pin. if the trigger is generated again while the counter is operating, the c ounter is cleared to 0000h and restarted. (the output of the toqn0 pin is inverted. the toqnk pin output s a high-level regardless of the status (high/low) when a trigger is generated.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tqnccrk register) count clock cycle cycle = (set value of tqnccr0 register + 1) count clock cycle duty factor = (set value of tqnccrk regist er)/(set value of tqnccr0 register + 1) the compare match request signal (inttqncc0) is generat ed when the 16-bit counter counts next time after its count value matches the value of the c cr0 buffer register, and the 16-bit count er is cleared to 0000h. the compare match interrupt request signal (inttqncck) is generated wh en the count value of the 16-bit counter matches the value of the ccrk buffer register. the value set to the tqnccrm register is transferred to the ccrm buffer register w hen the count value of the 16- bit counter matches the value of the ccr0 buffer re gister and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or se tting the software trigger (tqnctl1.tqnest bit) to 1 is used as the trigger. remark k = 1 to 3, m = 0 to 3, n = 0 to 2 figure 8-18. setting of registers in exte rnal trigger pulse output mode (1/3) (a) tmqn control register 0 (tqnctl0) 0/1 0 0 0 0 tqnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tqncks2 tqncks1 tqncks0 tqnce note the setting is invalid when the tqnctl1.tqneee bit = 1. remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 370 figure 8-18. setting of registers in exte rnal trigger pulse output mode (2/3) (b) tmqn control register 1 (tqnctl1) 0 0/1 0/1 0 0 tqnctl1 0: operate on count clock selected by tqncks0 to tqncks2 bits 1: count with external event input signal generate software trigger when 1 is written 010 tqnmd2 tqnmd1 tqnmd0 tqneee tqnest tqnsye 0, 1, 0: external trigger pulse output mode (c) tmqn i/o control register 0 (tqnioc0) 0/1 0/1 0/1 0/1 0/1 tqnioc0 0: disable toqn0 pin output 1: enable toqn0 pin output setting of output level while operation of toqn0 pin is disabled 0: low level 1: high level 0: disable toqn1 pin output 1: enable toqn1 pin output specification of active level of toqn1 pin output 0: active-high 1: active-low 0/1 0/1 0/1 note tqnoe1 tqnol0 tqnoe0 tqnol1 toqnk pin output 16-bit counter ? when tqnolk bit = 0 toqnk pin output 16-bit counter ? when tqnolk bit = 1 tqnoe3 tqnol2 tqnoe2 tqnol3 specification of active level of toqn3 pin output 0: active-high 1: active-low 0: disable toqn2 pin output 1: enable toqn2 pin output specification of active level of toqn2 pin output 0: active-high 1: active-low 0: disable toqn3 pin output 1: enable toqn3 pin output note clear this bit to 0 when the toqn0 pin is not used in the external trigger pulse output mode. remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 371 figure 8-18. setting of registers in exte rnal trigger pulse output mode (3/3) (d) tmqn i/o control register 2 (tqnioc2) 0 0 0 0 0/1 tqnioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tqnees0 tqnets1 tqnets0 tqnees1 (e) tmqn counter read buffer register (tqncnt) the value of the 16-bit counter can be read by reading the tqncnt register. (f) tmqn capture/compare register s 0 to 3 (tqnccr0 to tqnccr3) if d 0 is set to the tqnccr0 register, d 1 to the tqnccr1 register, d 2 to the tqnccr2 register, and d 3 , to the tqnccr3 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle toqn1 pin pwm waveform active level width = d 1 count clock cycle toqn2 pin pwm waveform active level width = d 2 count clock cycle toqn3 pin pwm waveform active level width = d 3 count clock cycle remarks 1. tmqn i/o control register 1 (tqnioc1) and tmqn option register 0 (tqnopt0) are not used in the external trigger pulse output mode. 2. updating tmqn capture/compare register 2 (tqnccr2) and tmqn capture/compare register 3 (tqnccr3) is validated by writing tmqn capture/compare register 1 (tqnccr1). 3. n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 372 (1) operation flow in extern al trigger pulse output mode figure 8-19. software processing flow in ex ternal trigger pulse output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tqnce bit external trigger input (tiqn0 pin input) tqnccr0 register ccr0 buffer register inttqncc0 signal toqn0 pin output (only when software trigger is used) tqnccr1 register ccr1 buffer register inttqncc1 signal toqn1 pin output tqnccr2 register ccr2 buffer register inttqncc2 signal toqn2 pin output tqnccr3 register ccr3 buffer register inttqncc3 signal toqn3 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 11 d 20 d 10 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 373 figure 8-19. software processing flow in ex ternal trigger pulse output mode (2/2) start <1> count operation start flow tqnce bit = 1 register initial setting tqnctl0 register (tqncks0 to tqncks2 bits) tqnctl1 register, tqnioc0 register, tqnioc2 register, tqnccr0 to tqnccr3 registers initial setting of these registers is performed before setting the tqnce bit to 1. writing of the tqnccr1 register must be performed when the set duty factor is only changed after writing the tqnccr2 and tqnccr3 registers. when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. tqnccr1 register writing of the same value is necessary only when the set duty factor of toqn2 and toqn3 pin outputs is changed. when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. only writing of the tqnccr1 register must be performed when the set duty factor is only changed. when counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. counting is stopped. the tqncks0 to tqncks2 bits can be set at the same time when counting is enabled (tqnce bit = 1). trigger wait status writing of the tqnccr1 register must be performed after writing the tqnccr0, tqnccr2, and tqnccr3 registers. when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer registers. tqnccr1 register writing of the same value is necessary only when the set cycle is changed. <2> tqnccr0 to tqnccr3 register setting change flow <3> tqnccr0 register setting change flow <4> tqnccr1 to tqnccr3 register setting change flow <5> tqnccr2, tqnccr3 register setting change flow <6> tqnccr1 register setting change flow <7> count operation stop flow tqnce bit = 0 setting of tqnccr2, tqnccr3 registers setting of tqnccr1 register setting of tqnccr2, tqnccr3 registers setting of tqnccr1 register stop setting of tqnccr1 register setting of tqnccr0 register setting of tqnccr1 register setting of tqnccr0, tqnccr2, and tqnccr3 registers tqnccr1 register when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 374 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tqnccr1 register last. rewrite the tqnccrk register after writing the tqnccr1 register after the inttqncc0 signal is detected. ffffh 16-bit counter 0000h tqnce bit external trigger input (tiqn0 pin input) d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tqnccr0 register ccr0 buffer register inttqncc0 signal tqnccr1 register ccr1 buffer register inttqncc1 signal toqn1 pin output tqnccr2 register ccr2 buffer register inttqncc2 signal toqn2 pin output tqnccr3 register ccr3 buffer register inttqncc3 signal toqn3 pin output toqn0 pin output (only when software trigger is used) d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 375 in order to transfer data from the tqnccrm register to the ccrm buffer register, the tqnccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tqnccr0 register, set the active level width to t he tqnccr2 and tqnccr3 registers, and then set an active level to the tqnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tqnccr0 register, and then write the same value to the tqnccr1 register. to change only the active level width (duty factor) of the pwm waveform, first set an active level to the tqnccr2 and tqnccr3 registers and then set an active level to the tqnccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toqn1 pin, only the tqnccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toqn2 and toqn3 pins, first set an active level width to the tqn ccr2 and tqnccr3 registers, and then write the same value to the tqnccr1 register. after data is written to the tqnccr1 register, the value written to the tqnccrm register is transferred to the ccrm buffer register in synchronization with clear ing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tqnccr0 to tqnccr3 registers again afte r writing the tqnccr1 register once, do so after the inttqncc0 signal is generated. otherwise, t he value of the ccrm buffer register may become undefined because timing of transferring data from t he tqnccrm register to the ccrm buffer register conflicts with writing the tqnccrm register. remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 376 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tqnccrk register to 0000h. if the set value of the tqnccr0 register is ffffh, the inttqncck signal is generated periodically. count clock 16-bit counter tqnce bit tqnccr0 register tqnccrk register inttqncc0 signal inttqncck signal toqnk pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 l remark k = 1 to 3, n = 0 to 2 to output a 100% waveform, set a value of (set value of tqnccr0 register + 1) to the tqnccrk register. if the set value of the tqnccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tqnce bit tqnccr0 register tqnccrk register inttqncc0 signal inttqncck signal toqnk pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 377 (c) conflict between trigger detection and match with ccrk buffer register if the trigger is detected immediately after the inttq ncck signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of t he toqnk pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccrk buffer register inttqncck signal toqnk pin output external trigger input (tiqn0 pin input) d k d k ? 1 0000 ffff 0000 shortened d k remark k = 1 to 3, n = 0 to 2 if the trigger is detected immediately before the in ttqncck signal is generated, the inttqncck signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the toqnk pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccrk buffer register inttqncck signal toqnk pin output external trigger input (tiqn0 pin input) d k d k ? 2d k ? 1d k 0000 ffff 0000 0001 extended remark k = 1 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 378 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the inttq ncc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the toqnk pin is extended by time from generation of the inttqncc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttqncc0 signal toqnk pin output external trigger input (tiqn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark k = 1 to 3, n = 0 to 2 if the trigger is detected immediately before the in ttqncc0 signal is generated, the inttqncc0 signal is not generated. the 16-bit counter is cleared to 0000h, the toqnk pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttqncc0 signal toqnk pin output external trigger input (tiqn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark k = 1 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 379 (e) generation timing of compare match interrupt request signal (inttqncck) the timing of generation of the inttqncck signal in the external trigger pulse output mode differs from the timing of other inttqncck signals; the inttqncck signal is generated when the count value of the 16-bit counter matches the value of the ccrk buffer register. count clock 16-bit counter ccrk buffer register toqnk pin output inttqncck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3, n = 0 to 2 usually, the inttqncck signal is generated in synchro nization with the next count up after the count value of the 16-bit counter matches the va lue of the ccrk buffer register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the toqnk pin. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 380 8.5.4 one-shot pulse output mode (tqnmd2 to tqnmd0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter q waits for a trigger when the tqnctl0.tqnce bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event counter q starts counting, and outputs a one-shot pulse from the toqn1 to toqn3 pins. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the toqn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 8-20. configuration in one-shot pulse output mode ccr0 buffer register tqnce bit tqnccr0 register clear match signal inttqncc0 signal toqn3 pin inttqncc3 signal toqn0 pin tiqn0 pin transfer s r s r tqnccr1 register ccr1 buffer register match signal toqn1 pin inttqncc1 signal transfer transfer s r tqnccr3 register ccr3 buffer register match signal transfer toqn2 pin inttqncc2 signal s r tqnccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 381 figure 8-21. basic timing in one-shot pulse output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) ffffh 16-bit counter 0000h tqnce bit external trigger input (tiqn0 pin input) tqnccr0 register inttqncc0 signal tqnccr2 register inttqncc2 signal toqn2 pin output tqnccr3 register inttqncc3 signal toqn3 pin output tqnccr1 register inttqncc1 signal toqn1 pin output toqn0 pin output (only when software trigger is used) remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 382 when the tqnce bit is set to 1, 16-bit timer/event counter q waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a o ne-shot pulse from the toqnk pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-s hot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tqnccrk register) count clock cycle active level width = (set value of tqnccr0 register ? set value of tqnccrk register + 1) count clock cycle the compare match interrupt request signal inttqncc0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal (inttqncck) is generated when the count value of the 16-bit counter matches the va lue of the ccrk buffer register. the valid edge of an external trigger input or setting the so ftware trigger (tqnctl1.tqnest bit) to 1 is used as the trigger. remark k = 1 to 3, n = 0 to 2 figure 8-22. setting of registers in one-shot pulse output mode (1/3) (a) tmqn control register 0 (tqnctl0) 0/1 0 0 0 0 tqnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tqncks2 tqncks1 tqncks0 tqnce (b) tmqn control register 1 (tqnctl1) 0 0/1 0/1 0 0 tqnctl1 0: operate on count clock selected by tqncks0 to tqncks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tqnmd2 tqnmd1 tqnmd0 tqneee tqnest tqnsye 0, 1, 1: one-shot pulse output mode note the setting is invalid when the tqnctl1.tqneee bit = 1. remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 383 figure 8-22. register setting in one-shot pulse output mode (2/3) (c) tmqn i/o control register 0 (tqnioc0) toqnk pin output 16-bit counter ? when tqnolk bit = 0 toqnk pin output 16-bit counter ? when tqnolk bit = 1 0/1 0/1 0/1 0/1 0/1 tqnioc0 0: disable toqn0 pin output 1: enable toqn0 pin output setting of output level while operation of toqn0 pin is disabled 0: low level 1: high level 0: disable toqn1 pin output 1: enable toqn1 pin output specification of active level of toqn1 pin output 0: active-high 1: active-low 0/1 0/1 0/1 note tqnoe1 tqnol0 tqnoe0 tqnol1 tqnoe3 tqnol2 tqnoe2 tqnol3 specification of active level of toqn3 pin output 0: active-high 1: active-low 0: disable toqn2 pin output 1: enable toqn2 pin output specification of active level of toqn2 pin output 0: active-high 1: active-low 0: disable toqn3 pin output 1: enable toqn3 pin output (d) tmqn i/o control register 2 (tqnioc2) 0 0 0 0 0/1 tqnioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tqnees0 tqnets1 tqnets0 tqnees1 note clear this bit to 0 when the toqn0 pin is not used in the one-shot pulse output mode. remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 384 figure 8-22. register setting in one-shot pulse output mode (3/3) (e) tmqn counter read buffer register (tqncnt) the value of the 16-bit counter can be read by reading the tqncnt register. (f) tmqn capture/compare register s 0 to 3 (tqnccr0 to tqnccr3) if d 0 is set to the tqnccr0 register and d k to the tqnccrk register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d k ? d 0 + 1) count clock cycle output delay period = (d k ) count clock cycle remarks 1. tmqn i/o control register 1 (tqnioc1) and tmqn option register 0 (tqnopt0) are not used in the one-shot pulse output mode. 2. k = 1 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 385 (1) operation flow in one-shot pulse output mode figure 8-23. software processing flow in one-shot pulse output mode (1/2) ffffh 16-bit counter 0000h tqnce bit external trigger input (tiqn0 pin input) tqnccr0 register inttqncc0 signal toqn0 pin output (only when software trigger is used) tqnccr1 register inttqncc1 signal toqn1 pin output tqnccr2 register inttqncc2 signal toqn2 pin output tqnccr3 register inttqncc3 signal toqn3 pin output d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 d 10 d 20 d 30 d 11 d 21 d 31 d 00 d 01 <3> <1> <2> remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 386 figure 8-23. software processing flow in one-shot pulse output mode (2/2) tqnce bit = 1 register initial setting tqnctl0 register (tqncks0 to tqncks2 bits) tqnctl1 register, tqnioc0 register, tqnioc2 register, tqnccr0 to tqnccr3 registers initial setting of these registers is performed before setting the tqnce bit to 1. the tqncks0 to tqncks2 bits can be set at the same time when counting has been started (tqnce bit = 1). trigger wait status start <1> count operation start flow tqnce bit = 0 count operation is stopped stop <3> count operation stop flow setting of tqnccr0 to tqnccr3 registers as rewriting the tqnccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttqnccr0 signal is recommended. <2> tqnccr0 to tqnccr3 register setting change flow remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 387 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tqnccrm register to change the set value of the tqnccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tqnccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. d k0 d k1 d 01 d 01 d 00 d k1 d 01 d k0 d k0 d k1 d 00 d 00 ffffh 16-bit counter 0000h tqnce bit external trigger input (tiqn0 pin input) tqnccr0 register inttqncc0 signal toqn0 pin output (only when software trigger is used) tqnccrk register inttqncck signal toqnk pin output delay (d k0 ) active level width (d 00 ? d k0 + 1) active level width (d 01 ? d k1 + 1) active level width (d 01 ? d k1 + 1) delay (d k1 ) delay (10000h + d k1 ) when the tqnccr0 register is rewritten from d 00 to d 01 and the tqnccrk register from d k0 to d k1 where d 00 > d 01 and d k0 > d k1 , if the tqnccrk register is rewritten when the count value of the 16-bit counter is greater than d k1 and less than d k0 and if the tqnccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter co unts up to ffffh and then counts up again from 0000h. when the count value matches d k1 , the counter generates the inttqncck signal and asserts the toqnk pin. when the count value matches d 01 , the counter generates the inttqncc0 signal, deasserts the toqnk pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark k = 1 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 388 (b) generation timing of compare match interrupt request signal (inttqncck) the generation timing of the inttqncck signal in the one-shot pulse out put mode is different from other inttqncck signals; the inttqncck signal is generat ed when the count value of the 16-bit counter matches the value of the tqnccrk register. count clock 16-bit counter tqnccrk register toqnk pin output inttqncck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 usually, the inttqncck signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tqnccrk register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the toqnk pin. remark k = 1 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 389 8.5.5 pwm output mode (tqnmd2 to tqnmd0 bits = 100) in the pwm output mode, a pwm waveform is output fr om the toqn1 to toqn3 pi ns when the tqnctl0.tqnce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the toqn0 pin. figure 8-24. configuration in pwm output mode ccr0 buffer register tqnce bit tqnccr0 register clear match signal inttqncc0 signal toqn3 pin inttqncc3 signal toqn0 pin transfer s r tqnccr1 register ccr1 buffer register match signal toqn1 pin inttqncc1 signal transfer transfer s r tqnccr3 register ccr3 buffer register match signal transfer toqn2 pin inttqncc2 signal s r tqnccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control output controller (rs-ff) output controller output controller (rs-ff) output controller (rs-ff) remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 390 figure 8-25. basic timing in pwm output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal toqn0 pin output tqnccr1 register inttqncc1 signal toqn1 pin output tqnccr2 register inttqncc2 signal toqn2 pin output tqnccr3 register inttqncc3 signal toqn3 pin output active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 3 ) active level width (d 3 ) active level width (d 3 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 391 when the tqnce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs pwm waveform from the toqnk pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tqnccrk register) count clock cycle cycle = (set value of tqnccr0 register + 1) count clock cycle duty factor = (set value of tqnccrk regist er)/(set value of tqnccr0 register + 1) the pwm waveform can be changed by rewriting the tqnccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal (inttqncc0) is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal (inttqncck) is generated when the count value of the 16-bit counter matches the value of the ccrk buffer register. remark k = 1 to 3, m = 0 to 3, n = 0 to 2 figure 8-26. setting of registers in pwm output mode (1/3) (a) tmqn control register 0 (tqnctl0) 0/1 0 0 0 0 tqnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tqncks2 tqncks1 tqncks0 tqnce (b) tmqn control register 1 (tqnctl1) 0 0 0/1 0 0 tqnctl1 100 tqnmd2 tqnmd1 tqnmd0 tqneee tqnest tqnsye 1, 0, 0: pwm output mode 0: operate on count clock selected by tqncks0 to tqncks2 bits 1: count external event input signal note the setting is invalid when the tqnctl1.tqneee bit = 1. remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 392 figure 8-26. setting of registers in pwm output mode (2/3) (c) tmqn i/o control register 0 (tqnioc0) toqnk pin output 16-bit counter ? when tqnolk bit = 0 toqnk pin output 16-bit counter ? when tqnolk bit = 1 0/1 0/1 0/1 0/1 0/1 tqnioc0 0: disable toqn0 pin output 1: enable toqn0 pin output setting of output level while operation of toqn0 pin is disabled 0: low level 1: high level 0: disable toqn1 pin output 1: enable toqn1 pin output specification of active level of toqn1 pin output 0: active-high 1: active-low 0/1 0/1 0/1 note tqnoe1 tqnol0 tqnoe0 tqnol1 tqnoe3 tqnol2 tqnoe2 tqnol3 specification of active level of toqn3 pin output 0: active-high 1: active-low 0: disable toqn2 pin output 1: enable toqn2 pin output specification of active level of toqn2 pin output 0: active-high 1: active-low 0: disable toqn3 pin output 1: enable toqn3 pin output (d) tmqn i/o control register 2 (tqnioc2) 0 0 0 0 0/1 tqnioc2 select valid edge of external event count input. 0/1 0 0 tqnees0 tqnets1 tqnets0 tqnees1 (e) tmqn counter read buffer register (tqncnt) the value of the 16-bit counter can be read by reading the tqncnt register. note clear this bit to 0 when the toqn0 pin is not used in the pwm output mode. remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 393 figure 8-26. register setting in pwm output mode (3/3) (f) tmqn capture/compare register s 0 to 3 (tqnccr0 to tqnccr3) if d 0 is set to the tqnccr0 register and d k to the tqnccrk register, t he cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d k count clock cycle remarks 1. tmqn i/o control register 1 (tqnioc1) and tmqn option register 0 (tqnopt0) are not used in the pwm output mode. 2. updating the tmqn capture/ compare register 2 (tqnccr2) and tmqn capture/compare register 3 (tqnccr3) is validated by writ ing the tmqn capture/compare register 1 (tqnccr1). 3. n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 394 (1) operation flow in pwm output mode figure 8-27. software processing flow in pwm output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register ccr0 buffer register inttqncc0 signal toqn0 pin output tqnccr1 register ccr1 buffer register inttqncc1 signal toqn1 pin output tqnccr2 register ccr2 buffer register inttqncc2 signal toqn2 pin output tqnccr3 register ccr3 buffer register inttqncc3 signal toqn3 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 10 d 20 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 395 figure 8-27. software processing flow in pwm output mode (2/2) start <1> count operation start flow tqnce bit = 1 register initial setting tqnctl0 register (tqncks0 to tqncks2 bits) tqnctl1 register, tqnioc0 register, tqnioc2 register, tqnccr0 to tqnccr3 registers initial setting of these registers is performed before setting the tqnce bit to 1. only writing of the tqnccr1 register must be performed when the set duty factor is only changed after writing the tqnccr2 and tqnccr3 registers. when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. tqnccr1 register writing of the same value is necessary only when the set duty factor of toqn2 and toqn3 pin outputs is changed. when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. only writing of the tqnccr1 register must be performed when the set duty factor is only changed. when counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. counting is stopped. the tqncks0 to tqncks2 bits can be set at the same time when counting is enabled (tqnce bit = 1). writing of the tqnccr1 register must be performed after writing the tqnccr0, tqnccr2, and tqnccr3 registers. when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer registers. tqnccr1 writing of the same value is necessary only when the set cycle is changed. <2> tqnccr0 to tqnccr3 register setting change flow <3> tqnccr0 register setting change flow <4> tqnccr1 to tqnccr3 register setting change flow <5> tqnccr2, tqnccr3 register setting change flow <6> tqnccr1 register setting change flow <7> count operation stop flow tqnce bit = 0 setting of tqnccr2, tqnccr3 registers setting of tqnccr1 register setting of tqnccr2, tqnccr3 registers setting of tqnccr1 register stop setting of tqnccr1 register setting of tqnccr0 register setting of tqnccr1 register setting of tqnccr0, tqnccr2, and tqnccr3 registers tqnccr1 register when the counter is cleared after setting, the value of the tqnccrm register is transferred to the ccrm buffer register. remark k = 1 to 3, m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 396 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tqnccr1 register last. rewrite the tqnccrk register after writing the tqnccr1 register after the inttqncc1 signal is detected. ffffh 16-bit counter 0000h tqnce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tqnccr0 register ccr0 buffer register inttqncc0 signal tqnccr1 register ccr1 buffer register inttqncc1 signal toqn1 pin output tqnccr2 register ccr2 buffer register inttqncc2 signal toqn2 pin output tqnccr3 register ccr3 buffer register inttqncc3 signal toqn3 pin output toqn0 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 397 to transfer data from the tqnccrm register to the ccrm buffer register, the tqnccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tqnccr0 register, set the active level width to t he tqnccr2 and tqnccr3 registers, and then set an active level width to the tqnccr1 register. to change only the active level width (duty factor) of pwm wave, first set the active level to the tqnccr2 and tqnccr3 registers, and then set an active level to the tqnccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toqn1 pin, only the tqnccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toqn2 and toqn3 pins, first set an active level width to the tqn ccr2 and tqnccr3 registers, and then write the same value to the tqnccr1 register. after the tqnccr1 register is written, the value wr itten to the tqnccrm register is transferred to the ccrm buffer register in synchronization with the timi ng of clearing the 16-bit counter, and is used as a value to be compared with the value of the 16-bit counter. to change only the cycle of the pwm waveform, first set a cycle to the tqnccr0 register, and then write the same value to the tqnccr1 register. to write the tqnccr0 to tqnccr3 registers again afte r writing the tqnccr1 register once, do so after the inttqncc0 signal is generated. otherwise, t he value of the ccrm buffer register may become undefined because the timing of transferring data from the tqnccrm register to the ccrm buffer register conflicts with writing the tqnccrm register. remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 398 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tqnccrk register to 0000h. if the set value of the tqnccr0 register is ffffh, the inttqncck signal is generated periodically. count clock 16-bit counter tqnce bit tqnccr0 register tqnccrk register inttqncc0 signal inttqncck signal toqnk pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3, n = 0 to 2 to output a 100% waveform, set a value of (set value of tqnccr0 register + 1) to the tqnccrk register. if the set value of the tqnccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tqnce bit tqnccr0 register tqnccrk register inttqncc0 signal inttqncck signal toqnk pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 399 (c) generation timing of compare match interrupt request signal (inttqncck) the timing of generation of the inttqncck signal in the pwm output mode differs from the timing of other inttqncck signals; the inttqncck signal is generat ed when the count value of the 16-bit counter matches the value of the tqnccrk register. count clock 16-bit counter ccrk buffer register toqnk pin output inttqncck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3, n = 0 to 2 usually, the inttqncck signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tqnccrk register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the toqnk pin. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 400 8.5.6 free-running timer mode (tqn md2 to tqnmd0 bits = 101) in the free-running timer mode, 16-bit timer/event counter q starts counting when the tqnctl0.tqnce bit is set to 1. at this time, the tqnccrm register can be used as a compare register or a captur e register, depending on the setting of the tqnopt0.tqnccs 0 and tqnopt0.tqnccs1 bits. remark m = 0 to 3, n = 0 to 2 figure 8-28. configuration in free-running timer mode toqn3 pin output toqn2 pin output toqn1 pin output toqn0 pin output inttqnov signal tqnccs0, tqnccs1 bits (capture/compare selection) inttqncc3 signal inttqncc2 signal inttqncc1 signal inttqncc0 signal tiqn3 pin (capture trigger input) tqnccr3 register (capture) tiqn0pin (external event count input/ capture trigger input) internal count clock tqnce bit tiqn1 pin (capture trigger input) tiqn2 pin (capture trigger input) tqnccr0 register (capture) tqnccr1 register (capture) tqnccr2 register (capture) tqnccr3 register (compare) tqnccr2 register (compare) tqnccr1 register (compare) 0 1 0 1 0 1 0 1 16-bit counter tqnccr0 register (compare) output controller output controller output controller output controller count clock selection edge detector edge detector edge detector edge detector edge detector chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 401 when the tqnce bit is set to 1, 16-bit timer/event counte r q starts counting, and the output signals of the toqn0 to toqn3 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tqnccrm register, a compare match interrupt request signal (inttq nccm) is generated, and the output signal of the toqnm pin is inverted. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttqnov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tqnopt0.tqnovf bi t) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tqnccrm register can be rewritten while the counter is ope rating. if it is rewritten, the new value is reflected at that time, and compared with the count value. figure 8-29. basic timing in free-r unning timer mode (compare function) d 10 d 20 d 30 d 00 d 20 d 31 d 31 d 30 d 00 d 11 d 11 d 21 d 01 d 11 d 21 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h toqn1 pin output tqnccr2 register inttqncc2 signal toqn2 pin output tqnccr3 register inttqncc3 signal toqn3 pin output inttqnov signal tqnovf bit toqn0 pin output tqnccr1 register inttqncc1 signal tqnce bit tqnccr0 register inttqncc0 signal d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 402 when the tqnce bit is set to 1, the 16-bit counter starts c ounting. when the valid edge input to the tiqnm pin is detected, the count val ue of the 16-bit counter is stored in the tqn ccrm register, and a capture interrupt request signal (inttqnccm) is generated. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttqnov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tqnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 8-30. basic timing in free-r unning timer mode (capture function) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tiqn2 pin input tqnccr2 register inttqncc2 signal tiqn3 pin input tqnccr3 register inttqncc3 signal inttqnov signal tqnovf bit tiqn1 pin input tqnccr1 register inttqncc1 signal tqnce bit tiqn0 pin input tqnccr0 register inttqncc0 signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 403 figure 8-31. register setting in free-running timer mode (1/3) (a) tmqn control register 0 (tqnctl0) 0/1 0 0 0 0 tqnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tqncks2 tqncks1 tqncks0 tqnce note the setting is invalid when the tqnctl1.tqneee bit = 1 (b) tmqn control register 1 (tqnctl1) 0 0 0/1 0 0 tqnctl1 101 tqnmd2 tqnmd1 tqnmd0 tqneee tqnest tqnsye 1, 0, 1: free-running mode 0: operate with count clock selected by tqncks0 to tqncks2 bits 1: count on external event count input signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 404 figure 8-31. register setting in free-running timer mode (2/3) (c) tmqn i/o control register 0 (tqnioc0) 0/1 0/1 0/1 0/1 0/1 tqnioc0 0: disable toqn0 pin output 1: enable toqn0 pin output 0: disable toqn1 pin output 1: enable toqn1 pin output setting of output level with operation of toqn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tqnoe1 tqnol0 tqnoe0 tqnol1 tqnoe3 tqnol2 tqnoe2 tqnol3 setting of output level with operation of toqn3 pin disabled 0: low level 1: high level 0: disable toqn2 pin output 1: enable toqn2 pin output setting of output level with operation of toqn2 pin disabled 0: low level 1: high level 0: disable toqn3 pin output 1: enable toqn3 pin output setting of output level with operation of toqn0 pin disabled 0: low level 1: high level (d) tmqn i/o control register 1 (tqnioc1) 0/1 0/1 0/1 0/1 0/1 tqnioc1 select valid edge of tiqn0 pin input select valid edge of tiqn1 pin input 0/1 0/1 0/1 tqnis2 tqnis1 tqnis0 tqnis3 tqnis6 tqnis5 tqnis4 tqnis7 select valid edge of tiqn2 pin input select valid edge of tiqn3 pin input remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 405 figure 8-31. register setting in free-running timer mode (3/3) (e) tmqn i/o control register 2 (tqnioc2) 0 0 0 0 0/1 tqnioc2 select valid edge of external event count input 0/1 0 0 tqnees0 tqnets1 tqnets0 tqnees1 (f) tmqn option register 0 (tqnopt0) 0/1 0/1 0/1 0/1 0 tqnopt0 overflow flag specifies if tqnccr0 register functions as capture or compare register specifies if tqnccr1 register functions as capture or compare register 0 0 0/1 tqnccs0 tqnovf tqnccs1 tqnccs2 tqnccs3 specifies if tqnccr2 register functions as capture or compare register specifies if tqnccr3 register functions as capture or compare register (g) tmqn counter read buffer register (tqncnt) the value of the 16-bit counter can be read by reading the tqncnt register. (h) tmqn capture/compare regist ers 0 to 3 (tqnccr0 to tqnccr3) these registers function as captur e registers or compare registers depending on the setting of the tqnopt0.tqnccsm bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to the tiqnm pin is detected. when the registers function as compare registers and when d m is set to the tqnccrm register, the inttqnccm signal is generated when the counter reaches (d m + 1), and the output signal of the toqnm pin is inverted. remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 406 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 8-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 10 d 20 d 30 d 00 d 10 d 20 d 30 d 00 d 11 d 31 d 01 d 21 d 21 d 11 d 11 d 31 d 01 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal toqn0 pin output tqnccr1 register inttqncc1 signal toqn1 pin output tqnccr2 register inttqncc2 signal toqn2 pin output tqnccr3 register inttqncc3 signal toqn3 pin output inttqnov signal tqnovf bit d 00 d 10 d 20 d 30 d 01 d 11 d 21 d 31 cleared to 0 by clr instruction set value changed set value changed set value changed set value changed cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 407 figure 8-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tqnce bit = 1 read tqnopt0 register (check overflow flag). register initial setting tqnctl0 register (tqncks0 to tqncks2 bits) tqnctl1 register, tqnioc0 register, tqnioc2 register, tqnopt0 register, tqnccr0 to tqnccr3 registers initial setting of these registers is performed before setting the tqnce bit to 1. the tqncks0 to tqncks2 bits can be set at the same time when counting has been started (tqnce bit = 1). start execute instruction to clear tqnovf bit (clr tqnovf). <1> count operation start flow <2> overflow flag clear flow tqnce bit = 0 counter is initialized and counting is stopped by clearing tqnce bit to 0. stop <3> count operation stop flow tqnovf bit = 1 no yes remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 408 (b) when using capture/compare register as capture register figure 8-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 0000 0000 0000 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tqnce bit tiqn2 pin input tqnccr2 register inttqncc2 signal tiqn3 pin input tqnccr3 register inttqncc3 signal inttqnov signal tqnovf bit tiqn1 pin input tqnccr1 register inttqncc1 signal tiqn0 pin input tqnccr0 register inttqncc0 signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 409 figure 8-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tqnce bit = 1 read tqnopt0 register (check overflow flag). register initial setting tqnctl0 register (tqncks0 to tqncks2 bits) tqnctl1 register, tqnioc1 register, tqnopt0 register initial setting of these registers is performed before setting the tqnce bit to 1. the tqncks0 to tqncks2 bits can be set at the same time when counting has been started (tqnce bit = 1). start execute instruction to clear tqnovf bit (clr tqnovf). <1> count operation start flow <2> overflow flag clear flow tqnce bit = 0 counter is initialized and counting is stopped by clearing tqnce bit to 0. stop <3> count operation stop flow tqnovf bit = 1 no yes remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 410 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter q is used as an in terval timer with the tqnccrm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time t he inttqnccm signal has been detected. d 00 d 10 d 20 d 01 d 30 d 12 d 03 d 22 d 31 d 21 d 23 d 02 d 13 ffffh 16-bit counter 0000h tqnce bit tqnccr0 register inttqncc0 signal toqn0 pin output tqnccr1 register inttqncc1 signal toqn1 pin output tqnccr2 register inttqncc2 signal toqn2 pin output tqnccr3 register inttqncc3 signal toqn3 pin output interval period (d 00 + 1) interval period (10000h + d 02 ? d 01 ) interval period (d 01 ? d 00 ) interval period (d 03 ? d 02 ) interval period (d 04 ? d 03 ) d 00 d 01 d 02 d 03 d 04 d 05 interval period (d 10 + 1) interval period (10000h + d 12 ? d 11 ) interval period (d 11 ? d 10 ) interval period (d 13 ? d 12 ) d 10 d 11 d 12 d 13 d 14 interval period (d 20 + 1) interval period (10000h + d 21 ? d 20 ) interval period (10000h + d 23 ? d 22 ) interval period (d 22 ? d 21 ) interval period (d 30 + 1) interval period (10000h + d 31 ? d 30) d 20 d 21 d 22 d 23 d 31 d 30 d 32 d 04 d 11 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 411 when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the co rresponding tqnccrm register must be re-set in the interrupt servicing that is executed when the inttqnccm signal is detected. the set value for re-setting the tqnccrm register c an be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 412 (b) pulse width measurement with capture register when pulse width measurement is performed with the tqnccrm register used as a capture register, software processing is necessary for reading the capt ure register each time the inttqnccm signal has been detected and for calculating an interval. d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 32 d 13 d 03 d 22 d 33 d 23 0000 pulse interval (10000h + d 01 ? d 00 ) pulse interval (10000h + d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) d 00 d 01 d 02 d 03 pulse interval (d 00 + 1) 0000 pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (d 13 ? d 12 ) d 10 d 11 d 12 d 13 pulse interval (d 10 + 1) 0000 pulse interval (10000h + d 21 ? d 20 ) pulse interval (20000h + d 22 ? d 21 ) pulse interval (d 23 ? d 22 ) d 20 d 21 d 23 d 22 pulse interval (d 20 + 1) 0000 pulse interval (10000h + d 31 ? d 30 ) pulse interval (10000h + d 32 ? d 31 ) pulse interval (10000h + d 33 ? d 32 ) d 30 d 31 d 32 d 33 pulse interval (d 30 + 1) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tqnce bit tiqn0 pin input tqnccr0 register inttqncc0 signal tiqn2 pin input tqnccr2 register inttqncc2 signal tiqn3 pin input tqnccr3 register inttqncc3 signal inttqnov signal tqnovf bit tiqn1 pin input tqnccr1 register inttqncc1 signal remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 413 when executing pulse width measurement in the fr ee-running timer mode, four pulse widths can be measured with one channel. to measure a pulse width, the pu lse width can be calculated by re ading the value of the tqnccrm register in synchronization with the inttqnccm si gnal, and calculating the difference between the read value and the previously read value. remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 414 (c) processing of overflow when two or more capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when tw o or more capture registers are used ffffh 16-bit counter 0000h tqnce bit tiqn0 pin input tqnccr0 register tiqn1 pin input tqnccr1 register inttqnov signal tqnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tqnccr0 register (setting of t he default value of t he tiqn0 pin input). <2> read the tqnccr1 register (setting of t he default value of t he tiqn1 pin input). <3> read the tqnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tqnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). remark n = 0 to 2 when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 415 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tqnce bit inttqnov signal tqnovf bit tqnovf0 flag note tiqn0 pin input tqnccr0 register tqnovf1 flag note tiqn1 pin input tqnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tqnovf0 and tqnovf1 flags are set on the internal ram by software. <1> read the tqnccr0 register (setting of t he default value of t he tiqn0 pin input). <2> read the tqnccr1 register (setting of t he default value of t he tiqn1 pin input). <3> an overflow occurs. set the tqnovf0 and tqnovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tqnccr0 register. read the tqnovf0 flag. if the tqno vf0 flag is 1, clear it to 0. because the tqnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tqnccr1 register. read the tqnovf1 flag. if the tqnovf1 flag is 1, clear it to 0 (the tqnovf0 flag is cleared in <4>, and the tqnovf1 flag remains 1). because the tqnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 416 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tqnce bit inttqnov signal tqnovf bit tqnovf0 flag note tiqn0 pin input tqnccr0 register tqnovf1 flag note tiqn1 pin input tqnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tqnovf0 and tqnovf1 flags are set on the internal ram by software. <1> read the tqnccr0 register (setting of t he default value of t he tiqn0 pin input). <2> read the tqnccr1 register (setting of t he default value of t he tiqn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tqnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tqnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tqnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tqnovf1 flag. if the tqno vf1 flag is 1, clear it to 0. because the tqnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 417 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tqnce bit tiqnm pin input tqnccrm register inttqnov signal tqnovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width in the free-running timer mode. <1> read the tqnccrm register (setting of t he default value of the tiqnm pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tqnccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. remark n = 0 to 2 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 418 example when capture trigger interval is long ffffh 16-bit counter 0000h tqnce bit tiqnm pin input tqnccrm register inttqnov signal tqnovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tqnccrm register (setting of t he default value of the tiqnm pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tqnccrm register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h). remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 419 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tqnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tqnopt0 register. to accurate ly detect an overflow, read the tqnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tqnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tqnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tqnovf bit) overflow flag (tqnovf bit) l h l remark n = 0 to 2 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 420 8.5.7 pulse width measurement mode (tqnmd2 to tqnmd0 bits = 110) in the pulse width measurement mode, 16-bit timer/even t counter q starts counting when the tqnctl0.tqnce bit is set to 1. each time the valid edge input to the tiqnm pi n has been detected, t he count value of t he 16-bit counter is stored in the tqnccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tqnccrm register after a capture interrupt request signal (inttqnccm) occurs. select either of the tiqn0 to tiqn3 pins as the capture trigger input pi n. specify ?no edge detected? by using the tqnioc1 register for the unused pins. when an external clock is used as the count clock, measur e the pulse width of the tiqnk pin because the external clock is fixed to the tiqn0 pin. at this time, clear the tqnioc1.tqnis1 and tqnioc1. tqnis0 bits to 00 (capture trigger input (tiqn0 pin): no edge detected). remark m = 0 to 3, n = 0 to 2, k = 1 to 3 figure 8-34. configuration in pulse width measurement mode inttqnov signal inttqncc0 signal inttqncc1 signal inttqncc2 signal inttqncc3 signal tiqn3 pin (capture trigger input) tqnccr3 register (capture) tiqn0 pin (external event count input/capture trigger input) internal count clock tqnce bit tiqn1 pin (capture trigger input) tiqn2 pin (capture trigger input) tqnccr0 register (capture) tqnccr1 register (capture) tqnccr2 register (capture) 16-bit counter clear edge detector edge detector edge detector edge detector edge detector count clock selection remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 421 figure 8-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tqnce bit tiqnm pin input tqnccrm register inttqnccm signal inttqnov signal tqnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark m = 0 to 3, n = 0 to 2 when the tqnce bit is set to 1, the 16-bit counter starts c ounting. when the valid edge input to the tiqnm pin is later detected, the count value of the 16-bit counter is stored in the tqnccrm register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttqnccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tiqnm pin even when the 16-bit counter coun ted up to ffffh, an overflow interrupt request signal (inttqnov) is generated at the next c ount clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tqnopt0.t qnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tqnovf bit set (1) count + captured value) count clock cycle remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 422 figure 8-36. register setting in pu lse width measurement mode (1/2) (a) tmqn control register 0 (tqnctl0) 0/1 0 0 0 0 tqnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tqncks2 tqncks1 tqncks0 tqnce note setting is invalid when the tqneee bit = 1. (b) tmqn control register 1 (tqnctl1) 0 0 0/1 0 0 tqnctl1 110 tqnmd2 tqnmd1 tqnmd0 tqneee tqnest tqnsye 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tqncks0 to tqncks2 bits 1: count external event count input signal (c) tmqn i/o control register 1 (tqnioc1) 0/1 0/1 0/1 0/1 0/1 tqnioc1 select valid edge of tiqn0 pin input select valid edge of tiqn1 pin input 0/1 0/1 0/1 tqnis2 tqnis1 tqnis0 tqnis3 tqnis6 tqnis5 tqnis4 tqnis7 select valid edge of tiqn2 pin input select valid edge of tiqn3 pin input (d) tmqn i/o control register 2 (tqnioc2) 0 0 0 0 0/1 tqnioc2 select valid edge of external event count input 0/1 0 0 tqnees0 tqnets1 tqnets0 tqnees1 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 423 figure 8-36. register setting in pu lse width measurement mode (2/2) (e) tmqn option register 0 (tqnopt0) 00000 tqnopt0 overflow flag 0 0 0/1 tqnovf tqnccs1 tqnccs2 tqnccs3 tqnccs0 (f) tmqn counter read buffer register (tqncnt) the value of the 16-bit counter can be read by reading the tqncnt register. (g) tmqn capture/compare regist ers 0 to 3 (tqnccr0 to tqnccr3) these registers store the count va lue of the 16-bit counter when the valid edge input to the tiqnm pin is detected. remarks 1. tmqn i/o control register 0 (tqnioc0) is not used in the pulse width measurement mode. 2. m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 424 (1) operation flow in pul se width measurement mode figure 8-37. software processing flow in pulse width measurement mode <1> <2> set tqnctl0 register (tqnce bit = 1) tqnce bit = 0 register initial setting tqnctl0 register (tqncks0 to tqncks2 bits), tqnctl1 register, tqnioc1 register, tqnioc2 register, tqnopt0 register initial setting of these registers is performed before setting the tqnce bit to 1. the tqncks0 to tqncks2 bits can be set at the same time when counting has been started (tqnce bit = 1). the counter is initialized and counting is stopped by clearing the tqnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tqnce bit tiqn0 pin input tqnccr0 register inttqncc0 signal d 0 0000h 0000h d 1 d 2 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 425 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tqnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tqnopt0 register. to accurate ly detect an overflow, read the tqnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tqnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tqnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tqnovf bit) overflow flag (tqnovf bit) l h l remark n = 0 to 2 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 426 8.5.8 triangular wave pwm mode (tqnmd2 to tqnmd0 = 111) in the triangular wave pwm mode, tmqn capture/compar e register k (tqnccrk) is used to set the duty factor, and tmqn capture/compare register 0 (tqnccr0) is used to set the cycle. by using these four registers and operating the timer, triangular wave pwm with a variable cycle is output. the value of the tqnccrm register can be rewritten when tqnce = 1. to stop timer q, clear tqnce to 0. the waveform of pwm is output from the toqnk pin. the toqn0 pin produces a toggle output when the value of the 16-bit counter matches the value of the tqnccr0 register and when the counter underflows. caution in the pwm mode, the capture function of the tqnccrm register cannot be used because this register can be used only as a compare register. remark n = 0 to 2, m = 0 to 3, k = 1 to 3 figure 8-38. timing of basic operation in triangular wave pwm mode (tqnoe0 = 1, tqnoe1 = 1, tqnoe2 = 1, tqnoe3 = 1, tqnol0 = 0, tqnol1 = 0, tqnol2 = 0, tqnol3 = 0) tqnce = 1 ffffh 16-bit counter toqn0 toqn1 inttqnov inttqncc0 match interrupt inttqncc1 match interrupt tqnccr0 toqn2 toqn3 inttqncc2 match interrupt inttqncc3 match interrupt 0000h d 00 d 00 d 30 d 30 d 20 d 20 d 10 d 10 tqnccr1 0000h d 10 tqnccr2 0000h d 20 tqnccr3 0000h d 30 d 00 d 30 d 30 d 20 d 20 d 10 d 00 d 30 d 30 d 20 d 20 remark n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 427 8.5.9 timer output operations the following table shows the operations and out put levels of the toqn0 to toqn3 pins. table 8-6. timer output control in each mode operation mode toqn0 pin toqn1 pin toqn2 pin toqn3 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output external trigger pulse output external trigger pulse output one-shot pulse output mode one-shot pulse output one-shot pulse output one-shot pulse output pwm output mode square wave output pwm output pwm output pwm output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? triangular wave pwm output mode square wave output triangular pwm output triangular pwm output triangular pwm output table 8-7. truth table of toqn0 to toqn3 pins under control of timer output control bits tqnioc0.tqnolm bit tqnioc0.tqnoem bit tqnctl0.tqnce bit level of toqnm pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark m = 0 to 3, n = 0 to 2 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 428 8.6 timer tuned operation function timer p and timer q have a timer tuned operation function. the timers that can be synchronized are listed in table 8-8. table 8-8. tuned operation mode of timers master timer slave timer tmp0 tmp1 ? tmp2 tmp3 tmq0 tmq1 tmq2 ? cautions 1. the tune d operation mode is enabled or disabled by the tpmctl1.tpmsye and tqnctl1.tqnsye bits. for tmq2, either or both tmq3 and tmq0 can be specified as slaves. 2. set the tuned operation mode usin g the following procedure. <1> set the tpmctl1.tpmsye and tqnctl1.tqnsye bits of the slave timer to enable the tuned operation. set the tpmctl1.tpmmd2 to tpmc tl1.tpmmd0 and tqnctl1.tpnmd2 to tqnctl1.tpnmd0 bits of the slave timer to the free-running mode <2> set the timer mode by using the tpnctl1.tpnmd2 to tpnctl1.tpnmd0 and tqnctl1.tpnmd2 to tqnctl1.tpnmd0 bits. at this time, do not set the tpnctl1.tpn sye and tqnctl1.tqnsye bits of the master timer. <3> set the compare register value of the master and slave timers. <4> set the tpmctl0.tpmce and tqnctl0.tq nce bits of the sl ave timer to enable operation on the internal operating clock. <5> set the tpnctl0.tpnce and tqnctl0.tqnc e bits of the master timer to enable operation on the internal operating clock. remark m = 1, 3 n = 0, 2 tables 8-9 and 8-10 show the timer modes t hat can be used in the tuned operation mode ( : settable, : not settable). table 8-9. timer modes usable in tuned operation mode master timer free-running mode pwm mode triangular wave pwm mode tmp0 tmp2 tmq1 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 429 table 8-10. timer output functions free-running mode pwm mode triangular wave pwm mode tuned channel timer pin tuning off tuning on tuning off tuning on tuning off tuning on top00 ppg toggle n/a tmp0 (master) top01 ppg pwm n/a top10 ppg toggle pwm n/a ch0 tmp1 (slave) top11 ppg pwm n/a top20 ppg toggle n/a tmp2 (master) top21 ppg pwm n/a top30 ppg toggle pwm n/a tmp3 (slave) top31 ppg pwm n/a toq00 ppg toggle pwm toggle n/a ch1 tmq0 (slave) toq01 to toq03 ppg pwm triangular wave pwm n/a toq10 ppg toggle toggle tmq1 (master) toq11 to toq13 ppg pwm triangular wave pwm toq20 ppg toggle pwm toggle triangular wave pwm ch2 tmq2 (slave) toq21 to toq23 ppg pwm triangular wave pwm remark the timing of transmitting data from the compare register of the master timer to the compare register of the slave timer is as follows. ppg: cpu write timing toggle, pwm, triangular wave pwm: timing at wh ich timer counter and compare register match topn0 and toqm0 (n = 0 to 3, m = 0 to 2) chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 430 figure 8-39. tuned operation image (tmp2, tmp3, tmq0) tmp2 top21 (pwm output) 16-bit timer/counter unit operation tmp2 (master ) + tmp3 (slave) + tmq0 (slave) tuned operation five pwm outputs are available when pwm is operated as a single unit. 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare tmp3 top31 (pwm output) tmq0 toq01 (pwm output) toq02 (pwm output) toq03 (pwm output) top21 (pwm output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top30 (pwm output) 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top31 (pwm output) toq01 (pwm output) toq00 (pwm output) toq02 (pwm output) toq03 (pwm output) seven pwm outputs are available when pwm is operated in tuned operation mode. chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 431 figure 8-40. basic operation timing of tuned pwm function (tmp2, tmp3, tmq0) top20 top21 top30 toq00 toq01 toq02 toq03 top31 tp2ccr0 tp2ce inttp2cc0 match interrupt inttp2cc1 match interrupt inttp3cc0 match interrupt inttp3cc1 match interrupt inttq0cc0 match interrupt inttq0cc1 match interrupt inttq0cc2 match interrupt inttq0cc3 match interrupt tp3ce tq0ce ffffh 0000h tmp2 16-bit counter d 00 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 tp2ccr1 d 10 tp3ccr0 d 20 tp3ccr1 d 30 tq0ccr0 d 40 tq0ccr1 d 50 tq0ccr2 d 60 tq0ccr3 d 70 chapter 8 16-bit timer/event counter q (tmq) preliminary user?s manual u17717ej2v0ud 432 8.7 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tqnccr0, tqnccr1, tqnccr2, and tq nccr3 registers if the capture trigger is input immediately after the tqnce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tqnce bit tqnccr0 register ffffh 0001h 0000h tiqn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tqnce bit tqnccr0 register tiqn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input remark n = 0 to 2 preliminary user?s manual u17717ej2v0ud 433 chapter 9 16-bit interval timer m (tmm) 9.1 overview ? interval function ? 8 clocks selectable ? 16-bit counter 1 (the 16-bit counter cannot be read during timer count operation.) ? compare register 1 (the compare register cannot be written during timer counter operation.) ? compare match interrupt 1 timer m supports only the clear & start mode. t he free-running timer mode is not supported. chapter 9 16-bit interval timer m (tmm) preliminary user?s manual u17717ej2v0ud 434 9.2 configuration tmm0 includes the following hardware. table 9-1. configuration of tmm0 item configuration timer register 16-bit counter register tmm0 compare register 0 (tm0cmp0) control register tmm0 control register 0 (tm0ctl0) figure 9-1. block diagram of tmm0 tm0ctl0 internal bus f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt controller 16-bit counter match clear inttm0eq0 tm0cmp0 tm0ce tm0cks2 tm0cks1tm0cks0 selector remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency intwt: watch timer interrupt request signal (1) 16-bit counter this is a 16-bit counter that counts the internal clock. the 16-bit counter cannot be read or written. (2) tmm0 compare register 0 (tm0cmp0) the tm0cmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset sets this register to 0000h. the same value can always be written to the tm0cmp0 register by software. tm0cmp0 register rewrite is prohibit ed when the tm0ctl0.tm0ce bit = 1. tm0cmp0 12108642 after reset: 0000h r/w address: fffff694h 14 0 13119753 15 1 chapter 9 16-bit interval timer m (tmm) preliminary user?s manual u17717ej2v0ud 435 9.3 register (1) tmm0 control register (tm0ctl0) the tm0ctl0 register is an 8-bit regist er that controls the tmm0 operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tm0ctl0 regist er by software. rewriting this register, except the tm0ce bit, is prohibited while the timer is operating. tm0ce tmm0 operation disabled (16-bit counter reset asynchronously). operation clock application stopped. tmm0 operation enabled. operation clock application started. tmm0 operation started. tm0ce 0 1 internal clock operation enable/disable specification tm0ctl0 0 0 0 0 tm0cks2 tm0cks1 tm0cks0 654321 after reset: 00h r/w address: fffff690h the internal clock control and internal circuit reset for tmm0 are performed asynchronously with the tm0ce bit. when the tm0ce bit is cleared to 0, the internal clock of tmm0 is disabled (fixed to low level) and 16-bit counter is reset asynchronously. 7 0 f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt tm0cks2 0 0 0 0 1 1 1 1 count clock selection tm0cks1 0 0 1 1 0 0 1 1 tm0cks0 0 1 0 1 0 1 0 1 cautions 1. set the tm0cks2 to tm 0cks0 bits when tm0ce bit = 0. when changing the value of tm0ce from 0 to 1, it is not possible to set the value of the tm0cks2 to tm0cks0 bits simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency chapter 9 16-bit interval timer m (tmm) preliminary user?s manual u17717ej2v0ud 436 9.4 operation caution do not set the tm0cmp0 register to ffffh. 9.4.1 interval timer mode in the interval timer mode, an interrupt request signal (i nttm0eq0) is generated at the specified interval if the tm0ctl0.tm0ce bit is set to 1. figure 9-2. configuration of interval timer 16-bit counter tm0cmp0 register tm0ce bit count clock selection clear match signal inttm0eq0 signal figure 9-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal d d d d d interval (d + 1) interval (d + 1) interval (d + 1) interval (d + 1) when the tm0ce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the c ounter starts counting. when the count value of the 16-bit counter matches the value of the tm0cmp0 register, the 16-bit counter is cleared to 0000h and a compare match interrupt request signal (inttm0eq0) is generated. the interval can be calculated by the following expression. interval = (set value of tm0cmp0 register + 1) count clock cycle chapter 9 16-bit interval timer m (tmm) preliminary user?s manual u17717ej2v0ud 437 figure 9-4. register setting for interval timer mode operation (a) tmm0 control register 0 (tm0ctl0) 0/1 0 0 0 0 tm0ctl0 0/1 0/1 0/1 tm0cks2 tm0cks1 tm0cks0 tm0ce 0: stop counting 1: enable counting select count clock (b) tmm0 compare register 0 (tm0cmp0) if the tm0cmp0 register is set to d, the interval is as follows. interval = (d + 1) count clock cycle chapter 9 16-bit interval timer m (tmm) preliminary user?s manual u17717ej2v0ud 438 (1) interval timer mode operation flow figure 9-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal d d d d <1> <2> tm0ce bit = 1 tm0ce bit = 0 register initial setting tm0ctl0 register (tm0cks0 to tm0cks2 bits) tm0cmp0 register initial setting of these registers is performed before setting the tm0ce bit to 1. the tm0cks0 to tm0cks2 bits can be set at the same time when counting has been started (tm0ce bit = 1). the counter is initialized and counting is stopped by clearing the tm0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow chapter 9 16-bit interval timer m (tmm) preliminary user?s manual u17717ej2v0ud 439 (2) interval timer mode operation timing caution do not set the tm0cmp0 register to ffffh. (a) operation if tm0cmp0 register is set to 0000h if the tm0cmp0 register is set to 0000h, the inttm 0eq0 signal is generated at each count clock. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tm0ce bit tm0cmp0 register inttm0eq0 signal 0000h interval time count clock cycle ffffh 0000h 0000h 0000h 0000h interval time count clock cycle (b) operation if tm0cmp0 register is set to n if the tm0cmp0 register is set to n, the 16-bit counter counts up to n. the counter is cleared to 0000h in synchronization with the next count-up timing and the inttm0eq0 signal is generated. ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal n interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle n remark 0000h < n < ffffh chapter 9 16-bit interval timer m (tmm) preliminary user?s manual u17717ej2v0ud 440 9.4.2 cautions (1) it takes the 16-bit counter up to the following time to start counting after the tm0ctl0.tm0ce bit is set to 1, depending on the count clock selected. selected count clock maximum time before counting start f xx 2/f xx f xx /2 6/f xx f xx /4 24/f xx f xx /64 128/f xx f xx /512 1024/f xx intwt second rising edge of intwt signal f r /8 16/f r f xt 2/f xt (2) rewriting the tm0cmp0 and tm0ctl0 regist ers is prohibited while tmm0 is operating. if these registers are rewritten while the tm0c e bit is 1, the operation cannot be guaranteed. if they are rewritten by mistake, clear the tm 0ctl0.tm0ce bit to 0, and re-set the registers. preliminary user?s manual u17717ej2v0ud 441 chapter 10 watch timer functions 10.1 functions the watch timer has the following functions. ? watch timer: an interrupt request signal (intwt) is gene rated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. ? interval timer: an interrupt request sig nal (intwti) is generated at set intervals. the watch timer and interval timer functions can be used at the same time. chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 442 10.2 configuration the block diagram of the watch timer is shown below. figure 10-1. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 f x f x /8 f x /4 f x /2 f x bgcs00 bgcs01 bgce0 3-bit prescaler 8-bit counter clear match f bgcs prsm0 register prscm0 register 1/2 2 internal bus clock control selector selector selector selector selector remark f x : main clock oscillation frequency f bgcs : watch timer source clock frequency f brg : watch timer count clock frequency f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt request signal intwti: interval timer interrupt request signal chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 443 (1) clock control this block controls supplying and stopping the operating clock (f x ) when the watch timer operates on the main clock. (2) 3-bit prescaler this prescaler divides f x to generate f x /2, f x /4, or f x /8. (3) 8-bit counter this 8-bit counter counts the source clock (f bgcs ). (4) 11-bit prescaler this prescaler divides f w to generate a clock of f w /2 4 to f w /2 11 . (5) 5-bit counter this counter counts f w or f w /2 9 , and generates a watch timer interrupt request signal at intervals of 2 4 /f w , 2 5 /f w , 2 12 /f w , or 2 14 /f w . (6) selector the watch timer has the following five selectors. ? selector that selects one of f x , f x /2, f x /4, or f x /8 as the source clock of the watch timer ? selector that selects the main clock (f x ) or subclock (f xt ) as the clock of the watch timer ? selector that selects f w or f w /2 9 as the count clock frequency of the 5-bit counter ? selector that selects 2 4 /f w , 2 13 /f w , 2 5 /f w , or 2 14 /f w as the intwt signal generation time interval ? selector that selects 2 4 /f w to 2 11 /f w as the interval timer interrupt re quest signal (intwti) generation time interval (7) prscm register this is an 8-bit compare register that sets the interval time. (8) prsm register this register controls clock supply to the watch timer. (9) wtm register this is an 8-bit register that contro ls the operation of the watch timer/in terval timer, and sets the interrupt request signal generation interval. chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 444 10.3 registers the following registers are provided for the watch timer. ? prescaler mode register 0 (prsm0) ? prescaler compare register 0 (prscm0) ? watch timer operation mode register (wtm) (1) prescaler mode register 0 (prsm0) the prsm0 register controls the generat ion of the watch timer count clock. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled enabled bgce0 0 1 main clock operation enable f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of watch timer source clock (f bgcs ) after reset: 00h r/w address: fffff8b0h cautions 1. do not change the values of the bgcs00 and bgcs01 bits during watch timer operation. 2. set the prsm0 register befo re setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 445 (2) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset sets this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 register during watc h timer operation. 2. set the prscm0 register before setting the prsm0.bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. the calculation for f brg is shown below. f brg = f bgcs /2n remark f bgcs : watch timer source clock set by the prsm0 register n: set value of prscm0 register = 1 to 256 however, n = 256 only when prscm0 register is set to 00h. chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 446 (3) watch timer operation mode register (wtm) the wtm register enables or di sables the count clock and operation of t he watch timer, sets the interval time of the prescaler, controls the operat ion of the 5-bit counter, and sets the set time of the watch flag. set the prsm0 register before setting the wtm register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.90 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.2 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 447 (2/2) 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply to operation with f w = 32.768 khz 3. f xt : subclock frequency 4. f brg : watch timer count clock frequency chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 448 10.4 operation 10.4.1 operation as watch timer the watch timer generates an interrupt request signal (int wt) at fixed time intervals. the watch timer operates using time intervals of 0.25 or 0.5 seconds wi th the subclock (32.768 khz) or main clock. the count operation starts when the wtm.wtm1 and wtm.wtm0 bits are set to 11. when the wtm0 bit is cleared to 0, the 11-bit prescaler and 5-bit co unter are cleared and the count operation stops. the time of the watch timer can be adjusted by clearin g the wtm1 bit to 0 and then the 5-bit counter when operating at the same time as the interval timer. at this time, an error of up to 15.6 ms may occur for the watch timer, but the interval timer is not affected. if the main clock is used as the count clock of the watc h timer, set the count clock using the prsm0.bgcs01 and bgcs00 bits, the 8-bit comparison value using the prscm0 register, and the count clock frequency (f brg ) of the watch timer to 32.768 khz. when the prsm0.bgce0 bit is set (1), f brg is supplied to the watch timer. f brg can be calculated by the following expression. f brg = f x /(2 m+1 n) to set f brg to 32.768 khz, perform the following calculat ion and set the bgcs01 and bgcs00 bits and the prscm0 register. <1> set n = f x /65,536. set m = 0. <2> when the value resulting from rounding up the first dec imal place of n is even, set n before the roundup as n/2 and m as m + 1. <3> repeat <2> until n is odd or m = 3. <4> set the value resulting from rounding up the first dec imal place of n to the prscm0 register and m to the bgcs01 and bgcs00 bits. example: when f x = 4.00 mhz <1> n = 4,000,000/65,536 = 61.03?, m = 0 <2>, <3> because n (round up the first decimal place) is odd, n = 61, m = 0. <4> set value of prscm0 register: 3dh (61), set value of bgcs01 and bgcs00 bits: 00 at this time, the actual f brg frequency is as follows. f brg = f x /(2 m+1 n) = 4,000,000/(2 61) = 32.787 khz remark m: division value (set value of bgcs01 and bgcs00 bits) = 0 to 3 n: set value of prscm0 register = 1 to 256 however, n = 256 only when prscm0 register is set to 00h. f x : main clock oscillation frequency chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 449 10.4.2 operation as in terval timer the watch timer can also be used as an interval time r that repeatedly generates an interrupt request signal (intwti) at intervals specifie d by a preset count value. the interval time can be selected by the wt m4 to wtm7 bits of the wtm register. table 10-1. interval time of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/fw 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/fw 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/fw 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/fw 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency chapter 10 watch timer functions preliminary user?s manual u17717ej2v0ud 450 figure 10-2. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remarks 1. when 0.5 seconds of the watch timer interrupt time is set. 2. f w : watch timer clock frequency values in parentheses apply to operation with f w = 32.768 khz. n: number of interval timer operations 10.4.3 cautions some time is required before the first watch timer interr upt request signal (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 1). figure 10-3. example of generation of watc h timer interrupt request signal (intwt) (when interrupt cycle = 0.5 s) it takes 0.515625 seconds (max.) for the first intwt signal to be generated (2 9 1/32768 = 0.015625 seconds longer (max.)). the intwt signal is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt preliminary user?s manual u17717ej2v0ud 451 chapter 11 functions of watchdog timer 2 11.1 functions watchdog timer 2 has the following functions. ? default-start watchdog timer note 1 reset mode: reset operation upon overflow of wa tchdog timer 2 (generation of wdt2res signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input selectable from main clock and intern al oscillation clock as the source clock notes 1. watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is executed via this function, or clear watchdog timer 2 once and stop it within the next interval time. also, write to the wdtm2 register for verifi cation purposes only once, even if the default settings (reset mode, interval time: f r /2 19 ) do not need to be changed. 2. for the non-maskable interrupt servicing due to a non-maskable interrupt request signal (intwdt2), see 16.2.2 (2) intwdt2 signal . chapter 11 functions of watchdog timer 2 preliminary user?s manual u17717ej2v0ud 452 11.2 configuration the following shows the block diagram of watchdog timer 2. figure 11-1. block diag ram of watchdog timer 2 f xx /2 9 clock input controller output controller wdt2res (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 16 to f xx /2 23 , f r /2 12 to f r /2 19 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear f r /2 3 remark f xx : main clock frequency f r : internal oscillation clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdtres2: watchdog timer 2 reset signal watchdog timer 2 includes the following hardware. table 11-1. configuration of watchdog timer 2 item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) chapter 11 functions of watchdog timer 2 preliminary user?s manual u17717ej2v0ud 453 11.3 registers (1) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and operation clock of watchdog timer 2. this register can be read or written in 8-bit units. this register can be read any number of times, but it can be written only once following reset release. reset sets this register to 67h. caution accessing the wdtm2 register is prohibited in th e following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2 signal) reset mode (generation of wdt2res signal) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 note note if the opb1 bit is set to 1 by using the option byte function (see chapter 25 ), the reset mode is fixed. cautions 1. for details of the wdcs20 to w dcs24 bits, see table 11-2 watchdog timer 2 clock selection. 2. if the wdtm2 register is rewritten twice after reset, an overflow signal is forcibly generated and the counter is reset. 3. to intentionally generate an overflow si gnal, write to the wdtm2 register only twice or write a value other than ach to the wdte register once. 4. to stop the operation of watchdog timer 2, wr ite 1fh to the wdtm2 register. if the opb1 bit is set to 1 by using the option byte function (see chapter 25), however, watchdog timer 2 cannot be stopped by any means other than reset. chapter 11 functions of watchdog timer 2 preliminary user?s manual u17717ej2v0ud 454 table 11-2. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs 20 selected clock 100 khz (min.) 200 khz (typ.) 400 khz (max.) 0 0 0 0 0 2 12 /f r 41.0 ms 20.5 ms 10.2 ms 0 0 0 0 1 2 13 /f r 81.9 ms 41.0 ms 20.5 ms 0 0 0 1 0 2 14 /f r 163.8 ms 81.9 ms 41.0 ms 0 0 0 1 1 2 15 /f r 327.7 ms 163.8 ms 81.9 ms 0 0 1 0 0 2 16 /f r 655.4 ms 327.7 ms 163.8 ms 0 0 1 0 1 2 17 /f r 1,310.7 ms 655.4 ms 327.7 ms 0 0 1 1 0 2 18 /f r 2,621.4 ms 1,310.7 ms 655.4 ms 0 0 1 1 1 2 19 /f r 5,242.9 ms 2,621.4 ms 1,310.7 ms f xx = 4 mhz f xx = 5 mhz 0 1 0 0 0 2 16 /f xx 16.4 ms 13.1 ms 0 1 0 0 1 2 17 /f xx 32.8 ms 26.2 ms 0 1 0 1 0 2 18 /f xx 65.5 ms 52.4 ms 0 1 0 1 1 2 19 /f xx 131.1 ms 104.9 ms 0 1 1 0 0 2 20 /f xx 262.1 ms 209.7 ms 0 1 1 0 1 2 21 /f xx 524.3 ms 419.4 ms 0 1 1 1 0 2 22 /f xx 1,048.6 ms 838.9 ms 0 1 1 1 1 2 23 /f xx 2,097.2 ms 1,677.7 ms 1 1 1 1 1 operation stopped caution if the opb1 bit is set to 1 by using the opti on byte function, the clock is fixed to the internal oscillation clock (f r ) (2 12 /f r to 2 19 /f r can be selected). for details, see chapter 25 option byte function. chapter 11 functions of watchdog timer 2 preliminary user?s manual u17717ej2v0ud 455 (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cleared and counting restarted by wr iting ?ach? to the wdte register. the wdte register can be read or written in 8-bit units. reset sets this register to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other than ?ach? is writ ten to the wdte register , an overflow signal is forcibly output. 2. when a 1-bit memory mani pulation instruction is execute d for the wdte register, an overflow signal is forcibly output. 3. to intentionally generate an overflow si gnal, write to the wdtm2 register only twice or write a value other than ach to the wdte register once. 4. the read value of the wdte register is ?9ah? (which differs from written value ?ach?). chapter 11 functions of watchdog timer 2 preliminary user?s manual u17717ej2v0ud 456 11.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following re set using byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm2 register using an 8-bit me mory manipulation instruction. after this, the operation of watchdog timer 2 cannot be stopped. the wdcs24 to wdcs20 bits of the wdtm 2 register are used to select the watchdog timer 2 loop detection time interval. writing ach to the wdte register cl ears the counter of watchdog timer 2 an d starts the count operation again. after the count operation has start ed, write ach to wdte within the loop detection time interval. if the time interval expires without ach being written to the wdte register, a reset signal (wdt2res) or a non- maskable interrupt request signal (intwdt2) is gener ated, depending on the set values of the wdm21 and wdtm2.wdm20 bits. when the wdtm2.wdm21 bit is set to 1 (reset mode), if a wdt overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will oc cur and the cpu clock will switch to the internal oscillation clock. to not use watchdog timer 2, wr ite 1fh to the wdtm2 register. for the non-maskable interrupt servicing while t he non-maskable interrupt request mode is set, see 16.2.2 (2) intwdt2 signal . preliminary user?s manual u17717ej2v0ud 457 chapter 12 a/d converter 12.1 overview the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 24 analog input signal channels (ani0 to ani23). the a/d converter has the following features. 10-bit resolution 24 channels successive approximation method operating voltage: av ref0 = 4.0 to 5.5 v analog input voltage: 0 v to av ref0 the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot scan mode the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode power-fail monitor function (conversion result compare function) 12.2 functions (1) 10-bit resolution a/d conversion an analog input channel is selected from ani0 to an i23, and an a/d conversion op eration is repeated at a resolution of 10 bits. each time a/d conversion has been completed, an interrupt request signal (intad) is generated. (2) power-fail detection function this function is used to detect a drop in the battery volt age. the result of a/d conversion (the value of the ada0crnh register) is compared with the value of t he ada0pft register, and the intad signal is generated only when a specified comparison condition is satisfied (n = 0 to 23). chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 458 12.3 configuration the block diagram of the a/d converter is shown below. figure 12-1. block diagram of a/d converter ani0 : : ani1 ani2 ani21 ani22 ani23 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller voltage comparator ada0pfm ada0cr0 ada0cr1 : : ada0cr2 ada0cr22 ada0cr23 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit ada0ets0 bit inttp2cc0 inttp2cc1 ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit selector selector ada0pfe bit ada0pfc bit sar voltage comparator & compare voltage generation dac the a/d converter includes the following hardware. table 12-1. configuration of a/d converter item configuration analog inputs 24 channels (ani0 to ani23 pins) registers successive approximation register (sar) a/d conversion result registers 0 to 23 (ada0cr0 to ada0cr23) a/d conversion result registers 0h to 23h (adcr0h to adcr23h): only higher 8 bits can be read control registers a/d converter mode registers 0 to 2 (ada0m0 to ada0m2) a/d converter channel specification register 0 (ada0s) power fail compare mode register (ada0pfm) power fail compare threshold value register (ada0pft) chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 459 (1) successive approximation register (sar) the sar register compares the voltage value of the analog input sign al with the output vo ltage of the compare voltage generation dac (compare voltage), and holds the co mparison result starting fr om the most significant bit (msb). when the comparison result has been held down to the le ast significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar register are transferred to the ada0crn register. remark n = 0 to 23 (2) a/d conversion result register n (ada0crn), a/d conversion result register nh (ada0crnh) the ada0crn register is a 16-bit regi ster that stores the a/d conversi on result. ada0arn consist of 24 registers and the a/d conversion result is stored in the 10 higher bits of the ad0crn register corresponding to analog input. (the lower 6 bits are fixed to 0.) (3) a/d converter mode register 0 (ada0m0) this register specifies the operation mode and cont rols the conversion operation by the a/d converter. (4) a/d converter mode register 1 (ada0m1) this register sets the conversion time of the analog input signal to be converted. (5) a/d converter mode register 2 (ada0m2) this register sets the hardware trigger mode. (6) a/d converter channel specification register (ada0s) this register sets the input port that inputs the analog voltage to be converted. (7) power-fail compare m ode register (ada0pfm) this register sets the power-fail monitor mode. (8) power-fail compare threshol d value register (ada0pft) the ada0pft register sets a threshold value that is compared with the value of a/d conversion result register nh (ada0crnh). the 8-bit data set to the ada0pft regi ster is compared with the hi gher 8 bits of the a/d conversion result register (ada0crnh). (9) controller the controller compares the result of the a/d conversion (the value of the ada0crnh register) with the value of the ada0pft register when a/d co nversion is completed or when the power-fail detection function is used, and generates the intad signal only when a spec ified comparison condition is satisfied. (10) sample & hold circuit the sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (11) voltage comparator the voltage comparator compares a voltage value that has been sample d and held with the voltage value of the compare voltag e generation dac. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 460 (12) compare voltage generation dac this compare voltage generation dac is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (13) ani0 to ani23 pins these are analog input pins for the 24 a/d converter channels and are used to input analog signals to be converted into digital signals. pins other than the one selected as the analog input by the ada0s register can be used as input port pins. cautions 1. make sure that the voltages input to the ani0 to ani23 pins do not exceed the rated values. in particular if a voltage of av ref0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. 2. the analog input pins (ani0 to ani23) functi on alternately as input port pins (p70 to p715, p120 to p127). if any of ani0 to ani23 is selected to execute a/ d conversion, do not execute an input instruction to ports 7 and 12 during conversion. if executed, the conversion resolution may be degraded. (14) av ref0 pin this is the pin used to input the reference voltage of t he a/d converter. always make the potential at this pin the same as that at the v dd pin even when the a/d converter is not us ed. the signals input to the ani0 to ani23 pins are converted to digital signal s based on the voltage applied between the av ref0 and av ss pins. (15) av ss pin this is the ground pin of t he a/d converter. always make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 461 12.4 registers the a/d converter is controlled by the following registers. ? a/d converter mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? a/d converter channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used. ? a/d conversion result register n (ada0crn) ? a/d conversion result register nh (ada0crnh) ? power-fail compare threshold value register (ada0pft) (1) a/d converter mode register 0 (ada0m0) the ada0m0 register is an 8-bit register that specif ies the operation mode and controls conversion operations. this register can be read or written in 8-bit or 1-bit units. however, ada0ef bit is read-only. reset sets this register to 00h. caution accessing the ada0m0 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 462 ada0ce ada0ce 0 1 stops a/d conversion enables a/d conversion a/d conversion control ada0m0 0 ada0md1 ada0md0 ada0ets1 ada0ets0 ada0tmd ada0ef ada0tmd 0 1 software trigger mode external trigger mode/timer trigger mode trigger mode specification ada0ef 0 1 a/d conversion stopped a/d conversion in progress a/d converter status display ada0md1 0 0 1 1 ada0md0 0 1 0 1 continuous select mode continuous scan mode setting prohibited one-shot scan mode specification of a/d converter operation mode ada0ets1 0 0 1 1 ada0ets0 0 1 0 1 no edge detection falling edge detection rising edge detection detection of both rising and falling edges specification of external trigger (adtrg pin) input valid edge after reset: 00h r/w address: fffff200h cautions 1. write operations to bit 0 are ignored. 2. changing the ada0m1 regist er value is prohibited while a/d conversion is enabled (ada0ce bit = 1). 3. if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written during a/d conversion (a da0ef bit = 1), the following will be performed according to the mode. ? in software trigger mode a/d conversion is stopped and started again from the beginning. ? in hardware trigger mode a/d conversion is stopped, and the trigger standby state is set. 4. when not using the a/d conver ter, stop the operation by setting the ada0ce bit to 0 to reduce the power consumption. 5. the resolution for the first con version of the data of the input pin immediately after the start of a/d conversion may be degraded. for details, see 12.6 (7) av ref0 pin. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 463 (2) a/d converter mode register 1 (ada0m1) the ada0m1 register is an 8-bit register that controls the conversion time specification. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: fffff201h 7 6 5 4 3 2 1 0 ada0m1 ada0hs1 0 0 0 ada0fr3 ada0fr2 ada0fr1 ada0fr0 cautions 1. be sure to cl ear bits 6 to 4 to ?0?. 2. be sure to set the ada0hs1 bit to ?1?. remark for a/d conversion time setting examples, see table 12-2 . table 12-2. conversion mode setting example ada0fr3 to ada0fr0 ada0hs1 3 2 1 0 a/d conversion time f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz a/d stabilization time note 0 0 0 0 31/f xx setting prohibited setting prohibited 7.75 s 16/f xx 0 0 0 1 62/f xx 3.10 s 3.88 s 15.50 s 31/f xx 0 0 1 0 93/f xx 4.65 s 5.81 s setting prohibited 47/f xx 0 0 1 1 124/f xx 6.20 s 7.75 s setting prohibited 50/f xx 0 1 0 0 155/f xx 7.75 s 9.69 s setting prohibited 50/f xx 0 1 0 1 186/f xx 9.30 s 11.63 s setting prohibited 50/f xx 0 1 1 0 217/f xx 10.85 s 13.56 s setting prohibited 50/f xx 0 1 1 1 248/f xx 12.40 s 15.50 s setting prohibited 50/f xx 1 0 0 0 279/f xx 13.95 s setting prohibited setting prohibited 50/f xx 1 0 0 1 310/f xx 15.50 s setting prohibited setting prohibited 50/f xx 1 0 1 0 341/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 0 1 1 372/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 1 0 0 403/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 1 0 1 434/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 1 1 0 465/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 1 1 1 1 496/f xx setting prohibited setting prohibited setting prohibited 50/f xx note when the ada0ce bit of the ada0m0 register is changed from 0 to 1 to secure the a/d converter stabilization time, the first a/d conversion starts after one of the above clock values is input. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 464 (3) a/d converter mode register 2 (ada0m2) the ada0m2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0m2 0 0 0 00 ada0tmd1 ada0tmd0 ada0tmd1 0 0 1 1 ada0tmd0 0 1 0 1 specification of hardware trigger mode external trigger mode (when adtrg pin valid edge detected) timer trigger mode 0 (when inttp2cc0 interrupt request generated) timer trigger mode 1 (when inttp2cc1 interrupt request generated) setting prohibited after reset: 00h r/w address: fffff203h 6543210 7 caution be sure to clear bits 7 to 2 to ?0?. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 465 (4) a/d converter channel specification register 0 (ada0s) the ada0s register specifies the pin that inputs the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: fffff202h 7 6 5 4 3 2 1 0 ada0s 0 0 0 ada0s4 ada0s3 ada0s2 ada0s1 ada0s0 ada0s4 ada0s3 ada0s2 ada0s1 ada0s0 select mode scan mode 0 0 0 0 0 ani0 ani0 0 0 0 0 1 ani1 ani0, ani1 0 0 0 1 0 ani2 ani0 to ani2 0 0 0 1 1 ani3 ani0 to ani3 0 0 1 0 0 ani4 ani0 to ani4 0 0 1 0 1 ani5 ani0 to ani5 0 0 1 1 0 ani6 ani0 to ani6 0 0 1 1 1 ani7 ani0 to ani7 0 1 0 0 0 ani8 ani0 to ani8 0 1 0 0 1 ani9 ani0 to ani9 0 1 0 1 0 ani10 ani0 to ani10 0 1 0 1 1 ani11 ani0 to ani11 0 1 1 0 0 ani12 ani0 to ani12 0 1 1 0 1 ani13 ani0 to ani13 0 1 1 1 0 ani14 ani0 to ani14 0 1 1 1 1 ani15 ani0 to ani15 1 0 0 0 0 ani16 ani0 to ani16 1 0 0 0 1 ani17 ani0 to ani17 1 0 0 1 0 ani18 ani0 to ani18 1 0 0 1 1 ani19 ani0 to ani19 1 0 1 0 0 ani20 ani0 to ani20 1 0 1 0 1 ani21 ani0 to ani21 1 0 1 1 0 ani22 ani0 to ani22 1 0 1 1 1 ani23 ani0 to ani23 other than above setting prohibited chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 466 (5) a/d conversion result regist ers n, nh (ada0crn, ada0crnh) the ada0crn and ada0crnh registers st ore the a/d conversion results. these registers are read-only, in 16-bit or 8-bit units. however, specify the ada0crn register for 16-bit access and the ada0crnh register for 8-bit access. the 10 bits of the conversion result are read from the higher 10 bits of the ada0crn register, and 0 is read from the lower 6 bits. the higher 8 bits of the conversion result are read from the ada0crnh register. caution accessing the ada0crn and ada0crnh regist ers is prohibited in the following statuses. for details, see 3.4.8 (2) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock after reset: undefined r address: ada0cr0 fffff210h, ada0cr1 fffff212h, ada0cr2 fffff214h, ada0cr3 fffff216h ada0cr4 fffff218h, ada0cr5 fffff21ah ada0cr6 fffff21ch, ada0cr7 fffff21eh ada0cr8 fffff220h, ada0cr9 fffff222h ada0cr10 fffff224h, ada0cr11 fffff226h ada0cr12 fffff228h, ada0cr13 fffff22ah ada0cr14 fffff22ch, ada0cr15 fffff22eh ada0cr16 fffff230h, ada0cr17 fffff232h ada0cr18 fffff234h, ada0cr19 fffff236h ada0cr20 fffff238h, ada0cr21 fffff23ah ada0cr22 fffff23ch, ada0cr23 fffff23eh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ada0crn ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0 0 0 0 0 0 after reset: undefined r address: ada0cr0h fffff211h, ada0cr1h fffff213h, ada0cr2h fffff215h, ada0cr3h fffff217h ada0cr4h fffff219h, ada0cr5h fffff21bh ada0cr6h fffff21dh, ada0cr7h fffff21fh ada0cr8h fffff221h, ada0cr9h fffff223h ada0cr10h fffff225h, ada0cr11h fffff227h ada0cr12h fffff229h, ada0cr13h fffff22bh ada0cr14h fffff22dh, ada0cr15h fffff22fh ada0cr16h fffff231h, ada0cr17h fffff233h ada0cr18h fffff235h, ada0cr19h fffff237h ada0cr20h fffff239h, ada0cr21h fffff23bh ada0cr22h fffff23dh, ada0cr23h fffff23fh 7 6 5 4 3 2 1 0 ada0crnh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 remark n = 0 to 23 caution a write operation to the ada0m0 and ad a0s registers may cause the contents of the ada0crn register to become undefined. a fter the conversion, read the conversion result before writing to the ada0m0 and ad a0s registers. correct conversion results may not be read if a sequence other than the above is used. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 467 the relationship between the analog volt age input to the analog input pins (a ni0 to ani23) and the a/d conversion result (ada0crn register) is as follows. v in sar = int ( av ref0 1,024 + 0.5) ada0cr note = sar 64 or, av ref0 av ref0 (sar ? 0.5) 1,024 v in < (sar + 0.5) 1,024 int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage ada0cr: value of ada0crn register note the lower 6 bits of the ada0crn register are fixed to 0. the following shows the relationship between the analo g input voltage and the a/d conversion results. figure 12-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results ada0crn sar ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 468 (6) power-fail compare m ode register (ada0pfm) the ada0pfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pfe power-fail compare disabled power-fail compare enabled ada0pfe 0 1 selection of power-fail compare enable/disable ada0pfm ada0pfc 00 00 0 0 generates an interrupt request signal (intad) when ada0crnh ada0pft generates an interrupt request signal (intad) when ada0crnh < ada0pft ada0pfc 0 1 selection of power-fail compare mode after reset: 00h r/w address: fffff204h 76 54 321 0 cautions 1. in the select mode, the 8-bit data set to the ada0pft regist er is compared with the value of the ada0crnh register specified by the ada0s register. if the result matches the condition specified by th e ada0pfc bit, the conversion result is stored in the ada0crn register and the intad signal is ge nerated. if it does not match, however, the interrupt signal is not generated. 2. in the scan mode, the 8-bit data set to the ada0pft register is compared with the contents of the ada0cr0h register. if th e result matches the c ondition specified by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison r esult, the scan operati on is continued and the conversion result is st ored in the ada0crn register until the scan operation is completed. however, the intad signal is not generated after th e scan operation has been completed. (7) power-fail compare thres hold value register (ada0pft) the ada0pft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pft after reset: 00h r/w address: fffff205h 76 54 321 0 chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 469 12.5 operation 12.5.1 basic operation <1> set the operation mode, trigger mode, and conversion time for executing a/d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter waits for a trigger in the external or timer trigger mode. <2> when a/d conversion is started, the voltage input to the selected anal og input channel is sampled by the sample & hold circuit. <3> when the sample & hold circuit samples the input cha nnel for a specific time, it enters the hold status, and holds the input analog voltage until a/d conversion is complete. <4> set bit 9 of the successive approximation register (sar) to set the compare voltage generation dac to (1/2) av ref0 . <5> the voltage difference between the compare volt age generation dac and the analog input voltage is compared by the voltage comparator. if th e analog input voltage is higher than (1/2) av ref0 , the msb of the sar register remains set. if it is lower than (1/2) av ref0 , the msb is reset. <6> next, bit 8 of the sar register is automatically set and the next comparison is started. depending on the value of bit 9, to which a result has been already set, the compare voltage generation dac is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 this compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage compare voltage: bit 8 = 1 analog input voltage compare voltage: bit 8 = 0 <7> this comparison is continued to bit 0 of the sar register. <8> when comparison of the 10 bits is complete, the valid di gital result is stored in t he sar register, which is then transferred to and stored in the ada0crn register. after that, an a/d conversion end interrupt request signal (intad) is generated. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 470 12.5.2 trigger mode the timing of starting the conversion oper ation is specified by setting a trigger mode. the trigger mode includes a software trigger mode and hardware trigger modes. the hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. the ada0m0.ada0tmd bit is us ed to set the trigger mode. the hardware trigger modes are set by the ada0m2.ada0tmd1 and ada0m2.ada0tmd0 bits. (1) software trigger mode when the ada0m0.ada0ce bit is set to 1, the signal of the analog input pin (ani0 to ani23) specified by the ada0s register is converted. when conversion is comple te, the result is stored in the ada0crn register. at the same time, the a/d conversion end interr upt request signal (intad) is generated. if the operation mode specified by the ada0m0.ada0md1 and ada0m0.ada0md0 bits is the continuous select/scan mode, the next conversion is started, unless the ada0ce bit is cleared to 0 after completion of the first conversion. conversion is performed once and ends if the operation mode is the one-shot select/scan mode. when conversion is started, the ada0m0.ada0ef bit is set to 1 (indicating that conversion is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft r egister is written during conversion, the conversion is aborted and started again from the beginning. (2) external trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani23) specified by the ada0s register is started when an external trigger is input (to the adtrg pin). which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both ri sing and falling edges) can be specified by using the ada0m0.ada0ets1 and ada0m0.ata0ets0 bits. when the ad a0ce bit is set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the re sult of conversion is stored in t he ada0crn register, regardless of whether the continuous select, contin uous scan, or one-shot scan mode is set as the operation mode by the ada0md1 and ada0md0 bits. at the same time, the intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conver sion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft r egister is written during the conversion operation, the conversion is not aborted, and the a/ d converter waits for the trigger again. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 471 (3) timer trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani23) specified by the ada0s register is started by the compare match interrupt request signal (inttp2cc0 or inttp2cc1) of the capture/compare register connected to the timer. the inttp2cc0 or inttp2cc1 signal is selected by the ada0tmd1 and ada0tmd0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. when the ada0ce bit is set to 1, the a/d co nverter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. when conversion is completed, regardless of whether th e continuous select, continuous scan, or one-shot scan mode is set as the operation mode by the ada0md 1 and ada0md0 bits, the result of the conversion is stored in the ada0crn register. at the same time, the intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conver sion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft r egister is written during conversion, the conversion is stopped and the a/d converter waits for the trigger again. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 472 12.5.3 operation mode three operation modes are available as the modes in which to set the ani0 to ani23 pins: continuous select mode, continuous scan mode, an d one-shot scan mode. the operation mode is selected by the ad a0m0.ada0md1 and ada0m0.ada0md0 bits. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is continuously converted into a digital value. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an ada0crn register on a one-to-one basis. each time a/d conversion is completed, the a/d conversion end interrupt reques t signal (intad) is generated. after completion of conversion, the next conversion is started, unless the ada0m0.ada0ce bit is cleared to 0 (n = 0 to 23). figure 12-3. timing example of continuous se lect mode operation (ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 (ani1) data 7 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. the result of each conversion is stored in the ada0cr n register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0 s register is complete, the intad signal is generated, and a/d conversion is started again from the ani0 pin, unless the ada0ce bit is cleared to 0 (n = 0 to 23). chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 473 figure 12-4. timing example of continuous s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 474 (3) one-shot scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. each conversion result is stored in the ada0crn regi ster corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s register is complete, the intad signal is generated. a/d conversion is stopped after it has been completed (n = 0 to 23). chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 475 figure 12-5. timing example of one-shot s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 (ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 476 12.5.4 power-fail compare mode the a/d conversion end interrupt re quest signal (intad) c an be controlled as foll ows by the ada0pfm and ada0pft registers. ? when the ada0pfm.ada0pfe bit = 0, the intad signal is generated each time conversion is completed (normal use of the a/d converter). ? when the ada0pfe bit = 1 and when t he ada0pfm.ada0pfc bit = 0, the va lue of the ada0crnh register is compared with the value of the ada0pft register wh en conversion is completed, and the intad signal is generated only if ada0crnh ada0pft. ? when the ada0pfe bit = 1 and when the ada0pfc bit = 1, the value of the ada0cr nh register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if ada0crnh < ada0pft. remark n = 0 to 23 in the power-fail compare mode, three modes are available as modes in which to set the ani0 to ani23 pins: continuous select mode, continuous scan mode, and one-shot scan mode. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 477 (1) continuous select mode in this mode, the result of converting the voltage of t he analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conver sion result is stored in the ada0crn register, and the intad signal is not generated. after completion of the fi rst conversion, the next conversion is started, unless the ada0m0.ada0ce bit is cleared to 0 (n = 0 to 23). figure 12-6. timing example of continuous select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 ( ani1) data 7 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 2 ( ani1) data 3 ( ani1) data 4 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 ada0pft unmatch ada0pft unmatch ada0pft match ada0pft match ada0pft match conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, the results of converting the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the ada0s register are st ored, and the set value of the ada0cr0h register of channel 0 is compared with the value of the ada0pft r egister. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion resu lt is stored in the ada0cr0 register, and the intad signal is generated. if it does not match, the conver sion result is stored in the ada0cr0 register, and the intad signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of sequentially converting the voltages on the analog input pins up to t he pin specified by the ada0 s register are continuously stored. after completion of conversion, the next conv ersion is started from the ani0 pin again, unless the ada0ce bit is cleared to 0. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 478 figure 12-7. timing example of continuous scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) data 7 ( ani2) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ada0pft unmatch ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 479 (3) one-shot scan mode in this mode, the results of converting the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the ada0s register are st ored, and the set value of the ada0cr0h register of channel 0 is compared with the set value of the ada0pf t register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conver sion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, the co nversion result is stored in the ada0cr0 register, and the intad0 signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of converting t he signals on the analog input pins s pecified by the ada0s register are sequentially stored. the conversion is stopped after it has been completed. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 480 figure 12-8. timing example of on e-shot scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 481 12.6 cautions (1) when a/d converter is not used when the a/d converter is not used, the power cons umption can be reduced by clearing the ada0m0.ada0ce bit to 0. (2) input range of ani0 to ani23 pins input the voltage within the specified range to the ani0 to ani23 pi ns. if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, the ani0 to ani23 pins must be effectively pr otected from noise. the influence of noise increases as the output impedance of the analog input sour ce becomes higher. to lower the noise, connecting an external capacitor as shown in figure 12-9 is recommended. figure 12-9. processing of analog input pin av ref0 v dd v ss av ss clamp with a diode with a low v f (0.3 v or less) if noise equal to or higher than av ref0 or equal to or lower than av ss may be generated. ani0 to ani23 (4) alternate i/o the analog input pins (ani0 to ani23) function alternately as port pins. when selecting one of the ani0 to ani23 pins to execute a/d conversion, do not execute an instruction to r ead an input port or write to an output port during conversion as the conversion resolution may drop. also the conversion resolution may drop at the pins set as output port pins during a/d conversion if the current flows due to the effect of the external circuit connected to the port pins. if a digital pulse is applied to a pin adjacent to t he pin whose input signal is being converted, the a/d conversion value may not be as expected due to the influence of coupling noise. therefore, do not apply a pulse to a pin adjacent to the pin undergoing a/d conversion. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 482 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the ada0s regi ster are changed. if the analog input pin is changed during a/d co nversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immediately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, cl ear the adif flag before resuming conversion. figure 12-10. generation timing of a/d conversion end interrupt request ada0s rewriting (anin conversion start) ada0s rewriting (anim conversion start) adif is set, but anim conversion does not end a/d conversion ada0crn intad anin anin anim anim anim anin anin anim remark n = 0 to 23 m = 0 to 23 (6) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 12-11. internal equi valent circuit of anin pin anin c in r in r in c in tbd tbd remark n = 0 to 23 chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 483 (7) av ref0 pin (a) the av ref0 pin is used as the power supply pin of the a/d converter and also supplies power to the alternate-function ports. in an application where a backup power supply is used, be sure to supply the same voltage as v dd to the av ref0 pin as shown in figure 12-12. (b) the av ref0 pin is also used as the reference voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion operation enable bit ada0ce has been set to 1). as a result, the conversion accuracy may drop. to avoid this, it is recommended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluctuation as shown in figure 12-12. (c) if the source supplying power to the av ref0 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. figure 12-12. av ref0 pin processing example av ref0 note av ss main power supply note parasitic inductance (8) reading ada0crn result when the ada0m0 to ada0m2 or ada0s register is wr itten, the contents of t he ada0crn register may be undefined. read the conversion result after completion of conversion and before writing to the ada0m0 to ada0m2 and ada0s registers. the correct conversion result may not be read at a timing different from the above. (9) a/d conversion result if there is noise at the analog input pins and at the reference voltage in put pins, that noise may generate an illegal conversion result. software processing will be neede d to avoid a negative effect on the system from this illegal conversion result. an example of this software processing is shown below. ? take the average result of a number of a/d conv ersions and use that as the a/d conversion result. ? execute a number of a/d conversions consecutively a nd use those results, omitti ng any exceptional results that may have been obtained. ? if an a/d conversion result that is judged to have generated a system malfunction is obtained, be sure to recheck the system malfunction before performing malfunction processing. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 484 (10) variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. to reduce the vari ation, take counteractive measures with the program such as averaging the a/d conversion results. (11) a/d conversion result hysteresis characteristics the successive comparison type a/d converter holds t he analog input voltage in the internal sample & hold capacitor and then performs a/d conversi on. after the a/d conversion ha s finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if th e voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous value. thus, even if t he conversion is performed at the same potential, the result may vary. ? when switching the analog input channel, hysteres is characteristics may appear where the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. thus, even if the conversion is perfo rmed at the same potential, the result may vary. chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 485 12.7 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that c an be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref0 ? 0)/100 = av ref0 /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics ta ble does not include the quantization error. figure 12-13. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 486 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 12-14. quantization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the actually measured analog input volt age and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 12-15. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 487 (5) full-scale error this is the difference between the actually measured analog input volt age and its theoretical value when the digital output changes from 1?110 to 1?111 (full scale ? 3/2 lsb). figure 12-16. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. th is error indicates the difference between the actually measured value and its theoretical value when a sp ecific code is output. this indicates the basic characteristics of the a/d conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from av ss to av ref0 . when the input voltage is increased or decreased, or when two or more channels are used, see 12.7 (2) overall error . figure 12-17. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output chapter 12 a/d converter preliminary user?s manual u17717ej2v0ud 488 (7) integral linearity error this error indicates the extent to which the conversion char acteristics differ from the ideal linear relationship. it indicates the maximum value of the difference between the actually measured valu e and its theoretical value where the zero-scale error and full-scale error are 0. figure 12-18. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after each trigger has been generated. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 12-19. sampling time sampling time conversion time preliminary user?s manual u17717ej2v0ud 489 chapter 13 asynchronous ser ial interface a (uarta) the v850es/hj2 includes asynchronous serial interface a (uarta). the number of channels differs depend ing on the product. table 13-1 sh ows the number of channels of each product. table 13-1. number of channels of asynchronous serial interface a product (part number) number of channels pd70f3709, 70f3710 3 channels (uarta0 to uarta2) pd70f3711, 70f3712 4 channels (uarta0 to uarta3) chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 490 13.1 features transfer rate: 300 bps to 312.5 kbps (using internal system clock of 20 mhz and dedicated baud rate generator) full-duplex communication: internal uartan receive data register (uanrx) internal uartan transmit data register (uantx) 2-pin configuration: txdan: transmit data output pin rxdan: receive data input pin reception error output function ? parity error ? framing error ? overrun error interrupt sources: 2 ? reception complete interrupt (intuanr): an interr upt is generated in the reception enabled status by oring three types of reception errors. it is also generated when receive data is transferred from the receive shift register to the receive data register afte r completion of serial transfer. ? transmission enable interrupt (intuant): this interr upt occurs upon transfer of transmit data from the transmit data register to the transmit shift register in the transmission enabled status. character length: 7, 8 bits parity function: odd, even, 0, none transmission stop bit: 1, 2 bits on-chip dedicated baud rate generator msb-/lsb-first transfer selectable transmit/receive data inverted input/output possible sbf (sync break field) transmission/reception in the li n (local interconnect network) communication format possible ? 13 to 20 bits selectable for sbf transmission ? recognition of 11 bits or more possible for sbf reception ? sbf reception flag provided remark n = 0 to 3 ( pd70f3711, 70f3712) n = 0 to 2 ( pd70f3709, 70f3710) chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 491 13.2 configuration the block diagram of the uartan is shown below. figure 13-1. block diagram of asyn chronous serial interface an internal bus internal bus uanotp0 uanctl0 uanstr uanctl1 uanctl2 receive shift register uanrx filter selector uantx transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intuanr intuant txdan rxdan f xx to f xx /2 10 ascka0 note reception unit transmission unit clock selector note uarta0 only remarks 1. n = 0 to 3 ( pd70f3711, 70f3712) n = 0 to 2 ( pd70f3709, 70f3710) 2. for the configuration of the baud rate generator, see figure 13-13 . uartan includes the following hardware units. table 13-2. configuration of uartan item configuration registers uartan control register 0 (uanctl0) uartan control register 1 (uanctl1) uartan control register 2 (uanctl2) uartan option control register 0 (uanopt0) uartan status register (uanstr) uartan receive shift register uartan receive data register (uanrx) uartan transmit shift register uartan transmit data register (uantx) chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 492 (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the uartan operation. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the input clock for the uartan. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register us ed to control the baud rate for the uartan. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register used to control serial transfer for the uartan. (5) uartan status register (uanstr) the uanstrn register consists of fl ags indicating the error contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error and is re set (to 0) by reading the uanstr register. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdan pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit register that holds receiv e data. when 7 characters are received, 0 is stored in the highest bit (when data is received lsb first). in the reception enabled status, receive data is transfe rred from the uartan receive shift register to the uanrx register in synchronization with the comple tion of shift-in processing of 1 frame. transfer to the uanrx register also causes the recept ion complete interrupt request signal (intuanr) to be output. (8) uartan transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the uantx register into serial data. when 1 byte of data is transferred from the uantx register, the shift register data is output from the txdan pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the uantx register. when data can be wri tten to the uantx register (when dat a of one frame is transferred from the uantx register to the uartan transmit shift regi ster), the transmission enable interrupt request signal (intuant) is generated. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 493 13.3 registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that c ontrols the uartan serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. (1/2) uanpwr disable uartan operation (uartan reset asynchronously) enable uartan operation uanpwr 0 1 uartan operation control uanctl0 uantxe uanrxe uandir uanps1 uanps0 uancl uansl 654321 after reset: 10h r/w address: ua0ctl0 fffffa00h, ua1ctl0 fffffa10h, ua2ctl0 fffffa20h, ua3ctl0 fffffa30h the uartan operation is controlled by the uanpwr bit. the txdan pin output is fixed to high level by clearing the uanpwr bit to 0 (fixed to low level if uanopt0.uantdl bit = 1). disable transmission operation enable transmission operation uantxe 0 1 transmission operation enable ? to start transmission, set the uanpwr bit to 1 and then set the uantxe bit to 1. to stop, transmission clear the uantxe bit to 0 and then uanpwr bit to 0. ? to initialize the transmission unit, clear the uantxe bit to 0, wait for two cycles of the base clock, and then set the uantxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 13.6 (1) (a) base clock ). disable reception operation enable reception operation uanrxe 0 1 reception operation enable ? to start reception, set the uanpwr bit to 1 and then set the uanrxe bit to 1. to stop reception, clear the uanrxe bit to 0 and then uanpwr bit to 0. ? to initialize the reception unit, clear the uanrxe bit to 0, wait for two periods of the base clock, and then set the uanrxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 13.6 (1) (a) base clock ). 7 0 remark n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 494 (2/2) 7 bits 8 bits uancl 0 1 specification of data character length of 1 frame of transmit/receive data this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. 1 bit 2 bits uansl 0 1 specification of length of stop bit for transmit data this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. this register is rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, the uanstr.uanpe bit is not set. when transmission and reception are performed in the lin format, clear the uanps1 and uanps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uanps1 0 0 1 1 parity selection during transmission parity selection during reception uanps0 0 1 0 1 msb-first transfer lsb-first transfer uandir 0 1 transfer direction selection this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. remark for details of parity, see 13.5.9 parity types and operations . chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 495 (2) uartan control register 1 (uanctl1) for details, see 13.6 (2) uartan control register 1 (uanctl1) . (3) uartan control register 2 (uanctl2) for details, see 13.6 (3) uartan control register 2 (uanctl2) . (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit regist er that controls the serial transfer operation of the uartan register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 14h. (1/2) uansrf when the uanctl0.uanpwr bit = uanctl0.uanrxe bit = 0 are set. also upon normal end of sbf reception. during sbf reception uansrf 0 1 sbf reception flag uanopt0 uansrt uanstt uansls2 uansls1 uansls0 uantdl uanrdl 654321 after reset: 14h r/w address: ua0opt0 fffffa03h, ua1opt0 fffffa13h, ua2opt0 fffffa23h, ua3opt0 fffffa33h sbf reception trigger uansrt 0 1 sbf reception trigger sbf (sync break field) reception is judged during lin communication. the uansrf bit is held at 1 when an sbf reception error occurs, and then sbf reception is started again. this is the sbf reception trigger bit during lin communication, and when read, ?0? is always read. for sbf reception, set the uansrt bit (to 1) to enable sbf reception. set the uansrt bit after setting the uanpwr bit = uanrxe bit = 1. this is the sbf transmission trigger bit during lin communication, and when read, ?0? is always read. set the uanstt bit after setting the uanpwr bit = uantxe bit = 1. sbf transmission trigger uanstt 0 1 sbf transmission trigger 7 0 ? ? caution do not set the uansrt and uanstt bits (to 1) during sbf reception (uansrf bit = 1). remark n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 496 (2/2) uansls2 1 1 1 0 0 0 0 1 uansls1 0 1 1 0 0 1 1 0 uansls0 1 0 1 0 1 0 1 0 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf transmit length selection the output level of the txdan pin can be inverted using the uantdl bit. this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0. this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0. normal output of transfer data inverted output of transfer data uantdl 0 1 transmit data level bit the input level of the rxdan pin can be inverted using the uanrdl bit. this register can be set when the uanpwr bit = 0 or the uanrxe bit = 0. normal input of transfer data inverted input of transfer data uanrdl 0 1 receive data level bit (5) uartan status register (uanstr) the uanstr register is an 8-bit register that displays t he uartan transfer status and reception error contents. this register can be read or written in 8-bit or 1-bi t units, but the uantsf bit is a read-only bit, while the uanpe, uanfe, and uanove bits can both be read and written. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). the initialization conditions are shown below. register/bit initialization conditions uanstr register ? reset ? uanctl0.uanpwr = 0 uantsf bit ? uanctl0.uantxe = 0 uanpe, uanfe, uanove bits ? 0 write ? uanctl0.uanrxe = 0 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 497 uantsf when the uanpwr bit = 0 or the uantxe bit = 0 has been set. when, following transfer completion, there was no next data transfer from uantx register write to uantx register uantsf 0 1 transfer status flag uanstr 0 0 0 0 uanpe uanfe uanove 654321 after reset: 00h r/w address: ua0str fffffa04h, ua1str fffffa14h, ua2str fffffa24h, ua3str fffffa34h the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit = 1. when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. when 0 has been written when parity of data and parity bit do not match during reception. uanpe 0 1 parity error flag the operation of the uanpe bit is controlled by the settings of the uanctl0.uanps1 and uanctl0.uanps0 bits. the uanpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. when the uanpwr bit = 0 or the uanrxe bit = 0 has been set when 0 has been written when no stop bit is detected during reception uanfe 0 1 framing error flag only the first bit of the receive data stop bits is checked, regardless of the value of the uanctl0.uansl bit. the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained . when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. when 0 has been written when receive data has been set to the uanrx register and the next receive operation is completed before that receive data has been read uanove 0 1 overrun error flag when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. the uanove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the value is retained . 7 0 remark n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 498 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer r egister that stores parallel data conver ted by the receive shift register. the data stored in the receive shift register is transfe rred to the uanrx register upon completion of reception of 1 byte of data. during lsb-first reception when the data length has been s pecified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uanrx register and the lsb always becomes 0. when an overrun error (uanove) occurs, the receive data at this time is not transferred to the uanrx register and is discarded. this register is read-only, in 8-bit units. in addition to reset input, the uanrx register can be set to ffh by clearing the uanctl0.uanpwr bit to 0. uanrx 654321 after reset: ffh r address: ua0rx fffffa06h, ua1rx fffffa16h, ua2rx fffffa26h, ua3rx fffffa36h 7 0 remark n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 (7) uartan transmit data register (uantx) the uantx register is an 8-bit register used to set transmit data. this register can be read or written in 8-bit units. reset sets this register to ffh. uantx 654321 after reset: ffh r/w address: ua0tx fffffa07h, ua1tx fffffa17h, ua2tx fffffa27h, ua3tx fffffa37h 7 0 remark n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 499 13.4 interrupt request signals the following two interrupt request signals are generated from uartan. ? reception complete interrupt request signal (intuanr) ? transmission enable interrupt request signal (intuant) the default priority for these two interrupt request signals is reception complete interrupt request signal then transmission enable interrupt request signal. table 13-3. interrupts and their default priorities interrupt priority reception complete high transmission enable low (1) reception complete interrupt request signal (intuanr) a reception complete interrupt request signal is output w hen data is shifted into the receive shift register and transferred to the uanrx register in the reception enabled status. when a reception complete interrupt request signal is rece ived and the data is read, read the uanstr register and check that the reception result is not an error. no reception complete interrupt request signal is generated in the reception disabled status. (2) transmission enable interr upt request signal (intuant) if transmit data is transferred from the uantx register to the uartan transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 500 13.5 operation 13.5.1 data format full-duplex serial data reception and transmission is performed. as shown in figure 13-2, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, s pecification of the stop bit length, and specification of msb/lsb-first transfer ar e performed using the uanctl0 register. moreover, control of uart output/inverted output for t he txdan bit is performed using the uanopt0.uantdl bit. ? start bit ..................1 bit ? character bits ........7 bits/8 bits ? parity bit ................even parity/odd parity/0 parity/no parity ? stop bit ..................1 bit/2 bits chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 501 figure 13-2. uarta transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdan inversion 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (d) 7-bit data length, lsb first, odd pa rity, 2 stop bits, transfer data: 36h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 parity bit stop bit stop bit (e) 8-bit data length, lsb first, no pa rity, 1 stop bit, transfer data: 87h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 502 13.5.2 sbf transmission/reception format the v850es/hj2 has an sbf (sync break field) transmissi on/reception control function to enable use of the lin function. remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communicat ion, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuators, and sensor s, and these are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame wit h baud rate information and the slave receives it and corrects the baud rate error. therefore, communicat ion is possible when the baud rate error in the slave is 15% or less. figures 13-3 and 13-4 outline the transmissi on and reception manipulations of lin. figure 13-3. lin transmissi on manipulation outline lin bus wake-up signal frame sync break field sync field identifier field data field data field check sum field intuant interrupt txdan (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. sbf output is performed by har dware. the output width is the bit length set by the uanopt0.uansbl2 to uanopt0.uansbl0 bits. if even finer output width adjustments are required, such adjustments can be performed us ing the uanctln.uanbrs7 to uanctln.uanbrs0 bits. 3. 80h transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. a transmission enable interrupt request signal (int uant) is output at the st art of each transmission. the intuant signal is also output at the start of each sbf transmission. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 503 figure 13-4. lin recepti on manipulation outline reception interrupt (intuanr) edge detection capture timer disable disable enable rxdan (input) enable note 2 13 bits sbf reception note 3 note 4 note 1 sf reception id reception data transmission data transmission note 5 data transmission lin bus wake-up signal frame sync break field sync field identifier field data field data field check sum field notes 1. the wakeup signal is sent by the pin edge detec tor, uartan is enabled, and the sbf reception mode is set. 2. the receive operation is performed until detection of the stop bit. upon detection of sbf reception of 11 or more bits, normal sbf reception end is judged, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, an sbf reception error is judged, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt request signal is output. the timer is enabled by an sbf reception complete interrupt. moreover, error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing and uartan receive shift register and data transfer of the uanrx register are not performed. the uartan receive shift register holds the initial value, ffh. 4. the rxdan pin is connected to ti (capture input) of the timer, the tran sfer rate is calculated, and the baud rate error is calculated. the value of the uanctl2 register obtained by correcting the baud rate error after dropping uarta enable is set again, causing the status to become the reception status. 5. check-sum field distinctions are made by softwar e. uartan is initialized following csf reception, and the processing for setting the sbf reception mode again is performed by software. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 504 13.5.3 sbf transmission when the uanctl0.uanpwr bit = uanctl0.uantxe bit = 1, the transmission enabled status is entered, and sbf transmission is started by setting (to 1) the sbf transmission trigger (uanopt0.uanstt bit). thereafter, a low level the width of bits 13 to 20 specif ied by the uanopt0.uansls2 to uanopt0.uansls0 bits is output. a transmission enable interrupt request signal (intuant) is generated upon sbf transmission start. following the end of sbf transmission, the uanstt bit is aut omatically cleared. thereafter, the uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the uantx register, or until the sbf transmission trigger (uanstt bit) is set. figure 13-5. sbf transmission intuant interrupt txdan 12345678910111213 stop bit setting of uanstt bit chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 505 13.5.4 sbf reception the reception enabled status is achieved by setting the uanctl0.uanpwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (uanopt0.uanstr bit) to 1. in the sbf reception wait status, similarly to the uart re ception wait status, the rxda n pin is monitored and start bit detection is performed. following detection of the start bit, rec eption is started and the in ternal counter counts up according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, normal processing is judged and a reception complete interrupt request signal (intuanr) is output. the uanopt0.uansrf bit is aut omatically cleared and sbf reception ends. error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing is not performed. moreover, data transfer of the uartan receive shift register and uanrx register is not performed and ffh, t he initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the sbf reception mode is returned to. the uansrf bit is not cleared at this time. figure 13-6. sbf reception (a) normal sbf reception (detection of stop bit in more than 10.5 bits) uansrf rxdan 123456 11.5 7 8 9 10 11 intuanr interrupt (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) uansrf rxdan 123456 10.5 78910 intuanr interrupt chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 506 13.5.5 uart transmission a high level is output to the txdan pin by setting the uanctl0.uanpwr bit to 1. next, the transmission enabled status is set by setting t he uanctl0.uantxe bit to 1, and transmission is started by writing transmit data to the uantx register. the st art bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) input pin is not pr ovided in uartan, use a port to check that reception is enabled at the transmit destination. the data in the uantx register is tr ansferred to the uartan transmit shift register upon the start of the transmit operation. a transmission enable interrupt request signal (intuant) is generated upon completion of transmission of the data of the uantx register to the uartan transmit shift register , and thereafter the contents of the uartan transmit shift register are output to the txdan pin. write of the next transmit data to t he uantx register is enabled after the intuant signal is generated. figure 13-7. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuant txdan remarks 1. lsb first 2. n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 507 13.5.6 continuous transmission procedure uartan can write the next transmit data to the uantx regist er when the uartan transmit shift register starts the shift operation. the transmit timing of the uartan transmi t shift register can be judged from the transmission enable interrupt request signal (intuant). an efficient communication rate is realized by writing t he data to be transmitted next to the uantx register during transfer. during continuous transmission, do not wr ite the next transmit data to the ua ntx register before a transmit request interrupt signal (intuant) is generated after transmit data is written to the uantx r egister and transferred to the uartan transmit shift register. if a value is written to t he uantx register before a transm it request interrupt signal is generated, the previously set transmit data is overwritten by the latest transmit data. caution when initializing transmis sions during the execution of contin uous transmissions, make sure that the uanstr.uantsf bit is 0, then perform the in itialization. transmit data that is initialized when the uantsf bit is 1 cannot be guaranteed. in the case of continuous transmission, the comm unication rate from the stop bit to the start bit of the next data is extended by tw o operating clocks from the normal rate. figure 13-8. continuous transmission processing flow start register settings uantx write yes yes no no occurrence of transmission interrupt? required number of writes performed? end chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 508 figure 13-9. continuous transmission operation timing (a) transmission start start data (1) data (1) txdan uantx transmission shift register intuant uantsf data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end start data (n ? 1) data (n ? 1) data (n ? 1) data (n) ff data (n) txdan uantx transmission shift register intuant uantsf uanpwr or uantxe bit parity stop stop start data (n) parity parity stop chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 509 13.5.7 uart reception the reception wait status is set by setting the uanctl0.uanpwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. in the reception wait status, the rxdan pin is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first the rising edge of the rxdan pin is detected and sampling is started at the falling edge. the start bit is recognized if the rxdan pin is low level at the start bit sampling point. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uart an receive shift register according to the set baud rate. when the reception complete interrupt request signal (i ntuanr) is output upon recepti on of the stop bit, the data of the uartan receive shift register is written to the uanr x register. however, if an overrun error (uanstr.uanove bit) occurs, the receive data at this time is not written to the uanrx register and is discarded. even if a parity error (uanstr.uanpe bit) or a framin g error (uanstr.uanfe bit) occurs during reception, reception continues until the recepti on position of the first stop bit, and in tuanr is output following reception completion. figure 13-10. uart reception start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuanr rxdan uanrx cautions 1. be sure to read the uanrx register even when a reception error occurs. if the uanrx register is not read, an overrun error occurs during r eception of the next data, and reception errors continue occurring indefinitely. 2. the operation during recepti on is performed assuming that th ere is only one stop bit. a second stop bit is ignored. 3. when reception is completed, read the uanrx register after the reception complete interrupt request signal (intuanr) has been generated, a nd clear the uanpwr or uanrxe bit to 0. if the uanpwr or uanrxe bit is cleared to 0 befo re the intuanr signal is generated, the read value of the uanrx register cannot be guaranteed. 4. if receive completion processing (intuanr signal generation) of uartan and the uanpwr bit = 0 or uanrxe bit = 0 conflict, the intuan r signal may be generated in spite of these being no data stored in the uanrx register. to complete reception without waiting intuanr signal generati on, be sure to clear (0) the interrupt request flag (uanrif) of the uanric register, after se tting (1) the interrupt mask flag (uanrmk) of the interrupt control register (uan ric) and then set (1) the uanpwr bit = 0 or uanrxe bit = 0. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 510 13.5.8 reception errors errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. data reception result error flags are set in the uanstr regi ster and a reception complete interrupt request signal (intuanr) is output when an error occurs. it is possible to ascertain which error occurred during reception by reading the contents of the uanstr register. clear the reception error flag by writing 0 to it after reading it. ? receive data read flow start no intuanr signal generated? error occurs? end yes no yes error processing read uanrx register read uanstr register caution when an intuanr signal is generated, the ua nstr register must be read to check for errors. ? reception error causes error flag reception error cause uanpe parity error received parity bit does not match the setting uanfe framing error stop bit not detected uanove overrun error reception of next data completed before data was read from receive buffer chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 511 when reception errors occur, perform the followin g procedures depending upon the kind of error. ? parity error if false data is received due to problems such as noi se in the reception line, discard the received data and retransmit. ? framing error a baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected. since this is a fatal error for the communication format, check the operation stop in the transmission side, perform initialization processing each other, and then start the communication again. ? overrun error since the next reception is completed before reading receiv e data, 1 frame of data is discarded. if this data was needed, do a retransmission. caution if a receive error interrupt occurs during cont inuous reception, read the contents of the uanstr register must be read before the next recepti on is completed, then pe rform error processing. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 512 13.5.9 parity types and operations caution when using the lin function, fix the uanps1 a nd uanps0 bits of the uanctl0 register to 00. the parity bit is used to detect bit errors in the comm unication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ?1? among the transmi t data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (ii) during reception the number of bits whose value is ?1? among the rec eption data, including the parit y bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ?1? among t he transmit data, including the parity bit, is controlled so that it is an odd number . the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (ii) during reception the number of bits whose value is ?1? among the receiv e data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity e rror occurs, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that ther e is no parity bit. no parity error occurs since there is no parity bit. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 513 13.5.10 receive data noise filter this filter samples the rxdan pin using the base clock of the prescaler output. when the same sampling value is read twice, the match det ector output changes and the rxdan signal is sampled as the input data. therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see figure 13-12 ). see 13.6 (1) (a) base clock regarding the base clock. moreover, since the circuit is as shown in figure 13-11, the processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. figure 13-11. noise filter circuit match detector in base clock (f uclk ) rxdan qin ld_en q internal signal c internal signal b in q internal signal a figure 13-12. timing of rxdan signal judged as noise internal signal b base clock rxdan (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 514 13.6 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartan. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. (1) baud rate generator configuration figure 13-13. configuration of baud rate generator f uclk selector uanpwr 8-bit counter match detector baud rate uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxen bits (or uanrxe bit) uanctl1: uancks3 to uancks0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 ascka0 note note only uarta0 is valid; setting uart a1 to uarta3 is prohibited. remarks 1. n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 2. f xx : main clock frequency 3. f uclk : base clock frequency (a) base clock when the uanctl0.uanpwr bit is 1, the cl ock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits is supplied to the 8-bit counter. this clock is called the base clock (f uclk ). (b) serial clock generation a serial clock can be generated by setting the uanctl1 register and the uanctl2 register (n = 0 to 3). the base clock is selected by uanctl1. uancks3 to uanctl1.uancks0 bits. the frequency division value for the 8-bit count er can be set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits. chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 515 (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the uartan base clock. this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the uanctl0.uanpwr bit to 0 before rewriting the uanctl1 register. 0 uanctl1 0 0 0 uancks3 uancks2 uancks1 uancks0 654321 after reset: 00h r/w address: ua0ctl1 fffffa01h, ua1ctl1 fffffa11h, ua2ctl1 fffffa21h, ua3ctl1 fffffa31h 7 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external clock note (ascka0 pin) setting prohibited uancks2 0 0 0 0 1 1 1 1 0 0 0 0 uancks3 0 0 0 0 0 0 0 0 1 1 1 1 base clock (f uclk ) selection uancks1 0 0 1 1 0 0 1 1 0 0 1 1 uancks0 0 1 0 1 0 1 0 1 0 1 0 1 other than above note only uarta0 is valid; setting uart a1 to uarta3 is prohibited. remarks 1. f xx : main clock frequency 2. n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 516 (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartan. this register can be read or written in 8-bit units. reset sets this register to ffh. caution clear the uanctl0.uanpwr bit to 0 or clear the uantxe and uanrxe bits to 00 before rewriting the uanctl2 register. uanbrs7 uanctl2 uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 654321 after reset ffh r/w address: ua0ctl2 fffffa02h, ua1ctl2 fffffa12h, ua2ctl2 fffffa22h, ua3ctl2 fffffa32h 7 0 uan brs7 0 0 0 0 : 1 1 1 1 uan brs6 0 0 0 0 : 1 1 1 1 uan brs5 0 0 0 0 : 1 1 1 1 uan brs4 0 0 0 0 : 1 1 1 1 uan brs3 0 0 0 0 : 1 1 1 1 uan brs2 0 1 1 1 : 1 1 1 1 uan brs1 0 0 1 : 0 0 1 1 uan brs0 0 1 0 : 0 1 0 1 default (k) 4 5 6 : 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /252 f uclk /253 f uclk /254 f uclk /255 setting prohibited remarks 1. f uclk : clock frequency selected by the uanctl1.uancks3 to uanctl1.uancks0 bits 2. n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 517 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] when using the internal clock, the equation will be as follows (when using the ascka0 pin as clock at uarta0, calculate using the above equation). baud rate = [bps] remark f uclk = frequency of base clock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits f xx : main clock frequency m = value set using the uanctl1.uancks3 to uanctl1.uancks0 bits (m = 0 to 10) k = value set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (k = 4 to 255) the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] = ? 1 100 [%] when using the internal clock, the equation will be as follows (when using the ascka0 pin as clock at uarta0, calculate the baud rate error using the above equation). error (%) = ? 1 100 [%] cautions 1. the baud rate erro r during transmission must be wit hin the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (5) allowable baud rate range dur ing reception. f uclk 2 k actual baud rate (baud rate with error) target baud rate (correct baud rate) f xx 2 m+1 k f uclk 2 k target baud rate f xx 2 m+1 k target baud rate chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 518 to set the baud rate, perform the following calculatio n and set the uanctl1 and uanctl2 registers (when using internal clock). <1> set k = f xx /(2 target baud rate). set m = 0. <2> set k = k/2 and m = m + 1 where k 256. <3> repeat <2> until k < 256. <4> roundup the first decimal place of k. if k = 256 by the roundup, perform <2> again (k will become 128). <5> set m to the uanctl1 register and k to the uanctl2 register. example: when f xx = 20 mhz and target baud rate = 153,600 bps <1> k = 20,000,000/(2 153,600) = 65.10?, m = 0 <2>, <3> k = 65.10? < 256, m = 0 <4> set value of uanctl2 register: k = 65 = 41h, set value of uanctl1 register: m = 0 actual baud rate = 20,000,000/(2 65) = 153,846 [bps] baud rate error = {20,000,000/(2 65 153,600) ? 1} 100 = 0.160 [%] the representative examples of baud rate settings are shown below. table 13-4. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) 300 08h 82h 0.16 0ah 1ah 0.16 07h 82h 0.16 600 07h 82h 0.16 0ah 0dh 0.16 06h 82h 0.16 1,200 06h 82h 0.16 09h 0dh 0.16 05h 82h 0.16 2,400 05h 82h 0.16 08h 0dh 0.16 04h 82h 0.16 4,800 04h 82h 0.16 07h 0dh 0.16 03h 82h 0.16 9,600 03h 82h 0.16 06h 0dh 0.16 02h 82h 0.16 19,200 02h 82h 0.16 05h 0dh 0.16 01h 82h 0.16 31,250 01h a0h 0.00 01h 80h 0.00 00h a0h 0.00 38,400 01h 82h 0.16 00h d0h 0.16 00h 82h 0.16 76,800 00h 82h 0.16 03h 0dh 0.16 00h 41h 0.16 153,600 00h 41h 0.16 02h 0dh 0.16 00h 21h ? 1.36 312,500 00h 20h 0.00 00h 1ah ? 1.54 00h 10h 0.00 remark f xx : main clock frequency err: baud rate error (%) chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 519 (5) allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error during reception must be set within the allowable error range using the following equation. figure 13-14. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartan transfer rate start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 3: pd70f3711, 70f3712 n = 0 to 2: pd70f3709, 70f3710 as shown in figure 13-14, the receive data latch timing is determined by the counter set using the uanctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. fl = (brate) ? 1 brate: uartan baud rate (n = 0 to 3) k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 3) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 520 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the following maximum allowable transfer rate yields the following. flmax = 11 fl ? fl = fl flmax = fl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartan and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 13-5. maximum/minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.52% ? 3.61% 20 +4.26% ? 4.30% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.72% remarks 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 3) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2 chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 521 (6) baud rate during cont inuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. however, timing initialization is performed via st art bit detection by the receiving side, so this has no influence on the transfer result. figure 13-15. transfer rate during continuous transfer start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of 2nd byte start bit bit 0 assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f uclk , we obtain the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + (2/f uclk ) chapter 13 asynchronous serial interface a (uarta) preliminary user?s manual u17717ej2v0ud 522 13.7 cautions (1) when the clock supply to uartan is stopped (for exam ple, in idle1, idle2, or stop mode), the operation stops with each register retaining the value it had i mmediately before the clock supply was stopped. the txdan pin output also holds and outputs the value it had immediately before the clock supply was stopped. however, the operation is not guarant eed after the clock supply is resumed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the uanctl0.uanpwr, uanctl0.uanrxen, and uanctl0.uantxen bits to 000. (2) the rxda1 and kr7 pins must not be used at the same ti me. to use the rxda1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). (3) in uartan, the interrupt caused by a communication error does not occur. when performing the transfer of transmit data and receive data using dma transfer, error proc essing cannot be performed even if errors (parity, overrun, framing) occur during transfer. either read the uanstr register after dma transfer has been completed to make sure that there are no errors, or read the uanstr register during communication to check for errors. (4) start up the uartan in the following sequence. <1> set the uanctl0.uanpwr bit to 1. <2> set the ports. <3> set the uanctl0.uantxe bit to 1, uanctl0.uanrxe bit to 1. (5) stop the uartan in the following sequence. <1> set the uanctl0.uantxe bit to 0, uanctl0.uanrxe bit to 0. <2> set the ports and set the uanctl0.uanpwr bit to 0 (it is not a problem if port setting is not changed). (6) in transmit mode (uanctl0.uanpwr bit = 1 and uanctl0.uantxe bit = 1), do not overwrite the same value to the uantx register by software because transmission starts by writing to this register. to transmit the same value continuously, overwrite the same value. (7) in continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks more than usual. however, the reception side init ializes the timing by detecting the start bit, so the reception result is not affected. (8) if the break command is executed in the on-chip debu g (ocd) mode and if uart receives data, an overrun error occurs. preliminary user?s manual u17717ej2v0ud 523 chapter 14 3-wire variable-length serial i/o (csib) the v850es/hj2 has three channels of 3-wire serial interface (csib). 14.1 features transfer rate: 8 mbps to 4.9 kbps (f xx = 20 mhz, using internal clock) master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface interrupt request signals (intcbnt, intcbnr) 3 serial clock and data phase switchable transfer data length selectable in 1-bit units between 8 and 16 bits transfer data msb-first/lsb-first switchable 3-wire transfer sobn: serial data output sibn: serial data input sckbn: serial clock i/o transmission mode, reception mode, and transmission/reception mode specifiable remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 524 14.2 configuration the following shows the block diagram of csibn. figure 14-1. block diagram of csibn internal bus cbnctl2 cbnctl0 cbnstr controller intcbnr sobn intcbnt cbntx so latch phase control shift register cbnrx cbnctl1 phase control sibn note f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 sckbn selector note n = 0: f brg n = 1: top01 n = 2: f xx /128 remark n = 0 to 2 csibn includes the following hardware. table 14-1. configuration of csibn item configuration registers csibn receive data register (cbnrx) csibn transmit data register (cbntx) control registers csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) csibn status register (cbnstr) chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 525 (1) csibn receive data register (cbnrx) the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by reading the cbnrx register in the reception enabled status. if the transfer data length is 8 bits, the lower 8 bits of th is register are read-only in 8-bit units as the cbnrxl register. reset sets this register to 0000h. in addition to reset input, the cbnrx register can be in itialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. after reset: 0000h r address: cb0rx fffffd04h, cb1rx fffffd14h, cb2rx fffffd24h cbnrx (n = 0 to 2) (2) csib transmit data register (cbntx) the cbntx register is a 16-bit buffer regist er used to write the csibn transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to t he cbntx register in the transmission enabled status. if the transfer data length is 8 bits, the lower 8 bits of th is register are read-only in 8-bit units as the cbntxl register. reset sets this register to 0000h. after reset 0000h r/w address: cb0tx fffffd06h, cb1tx fffffd16h, cb2tx fffffd26h cbntx (n = 0 to 2) remark the communication start conditions are shown below. transmission mode (cbntxe bit = 1, cbnrxe bit = 0): write to cbntx register transmission/reception mode (cbntxe bit = 1, cb nrxe bit = 1): write to cbntx register reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 526 14.3 registers the following registers are used to control csibn. ? csibn control register 0 (cbnctl0) ? csibn control register 1 (cbnctl1) ? csibn control register 2 (cbnctl2) ? csibn status register (cbnstr) (1) csibn control register 0 (cbnctl0) cbnctl0 is a register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. (1/3) cbnpwr disable csibn operation and reset the cbnstr register enable csibn operation cbnpwr 0 1 specification of csibn operation disable/enable cbnctl0 (n = 0 to 2) cbntxe note cbnrxe note cbndir note 00 cbntms note cbnsce after reset: 01h r/w address: cb0ctl0 fffffd00h, cb1ctl0 fffffd10h, cb2ctl0 fffffd20h the cbnpwr bit controls the csibn operation and resets the internal circuit. disable transmit operation enable transmit operation cbntxe note 0 1 specification of transmit operation disable/enable the sobn output is low level when the cbntxe bit is 0. when the cbnrxe bit is cleared to 0, no reception complete interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (cbnrx register) is not updated. disable receive operation enable receive operation cbnrxe note 0 1 specification of receive operation disable/enable note these bits can only be rewritten when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time as rewriting these bits. caution to forcibly suspend transmission/recepti on, clear the cbnpwr bit instead of the cbnrxe bit to 0. at this time, the clock output is stopped. chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 527 (2/3) single transfer mode continuous transfer mode cbntms note 0 1 transfer mode specification [in single transfer mode] the reception complete interrupt request signal (intcbnr) is generated. even if transmission is enabled (cbntxe bit = 1), the transmission enable interrupt request signal (intcbnt) is not generated. if the next transmit data is written during communication (cbnstr.cbntsf bit = 1), it is ignored and the next communication is not started. also, if reception-only communication is set (cbntxe bit = 0, cbnrxe bit = 1), the next communication is not started even if the receive data is read during communication (cbnstr. cbbtsf bit = 1). [in continuous transfer mode] the continuous transmission is enabled by writing the next transmit data during communication (cbnstr.cbntsf bit = 1). writing the next transmission data is enabled after a transmission enable interrupt (intcbnt) occurrence. if reception-only communication is set (cbntxe bit = 0, cbnrxe bit = 1) in the continuous transfer mode, the next reception is started continuously after a reception complete interrupt (intcbnr) regardless of the read operation of the cbnrx register. therefore, read immediately the receive data from the cbnrx register. if this read operation is delayed, an overrun error (cbnove bit = 1) occurs. cbndir note 0 1 specification of transfer direction mode (msb/lsb) msb-first transfer lsb-first transfer note these bits can only be rewritten when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time as rewriting these bits. chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 528 (3/3) communication start trigger invalid communication start trigger valid cbnsce 0 1 specification of start transfer disable/enable in master mode this bit enables or disables the communication start trigger. (a) in single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode the setting of the cbnsce bit has no influence on communication operation. (b) in single reception mode clear the cbnsce bit to 0 before reading the last receive data because reception is started by reading the receive data (cbnrx register) to disable the reception startup note 1 . (c) in continuous reception mode clear the cbnsce bit to 0 one communication clock before reception of the last data is completed to disable the reception startup after the last data is received note 2 . in slave mode this bit enables or disables the communication start trigger. set the cbnsce bit to 1. [usage of cbnsce bit] in single reception mode <1>when reception of the last data is completed by intcbnr interrupt servicing, clear the cbnsce bit to 0 before reading the cbnrx register. <2>after confirming the cbnstr.cbntsf bit = 0, clear the cbnrxe bit to 0 to disable reception. to continue reception, set the cbnsce bit to 1 to start up the next reception by dummy-reading the cbnrx register. in continuous reception mode <1>clear the cbnsce bit to 0 during the reception of the last data by intcbnr interrupt servicing. <2>read the cbnrx register. <3>read the last reception data by reading the cbnrx register after acknowledging the cbntir interrupt. <4>after confirming the cbnstr.cbntsf bit = 0, clear the cbnrxe bit to 0 to disable reception. to continue reception, set the cbnsce bit to 1 to wait for the next reception by dummy-reading the cbnrx register. notes 1. if the cbnsce bit is read while it is 1, the next communication operation is started. 2. the cbnsce bit is not cleared to 0 one communica tion clock before the completion of the last data reception, the next communication operation is automatically started. caution be sure to clear bits 3 and 2 to ?0?. chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 529 (2) csibn control register 1 (cbnctl1) cbnctl1 is an 8-bit register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution the cbnctl1 register can be rewritte n only when the cbnc tl0.cbnpwr bit = 0. 0 cbnckp 0 0 1 1 specification of data transmission/ reception timing in relation to sckbn cbnctl1 (n = 0 to 2) 0 cbndap 0 1 0 1 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 after reset 00h r/w address: cb0ctl1 fffffd01h, cb1ctl1 fffffd11h, cb2ctl1 fffffd21h cbncks2 0 0 0 0 1 1 1 1 cbncks1 0 0 1 1 0 0 1 1 cbncks0 0 1 0 1 0 1 0 1 communication clock f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f brg note external clock (sckbn) master mode master mode master mode master mode master mode master mode master mode slave mode mode cbnctl1 (n = 0 to 2) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) communication type 1 communication type 2 communication type 3 communication type 4 n = 0 n = 1 n = 2 tmp0 (top01) f xx /128 note for details, see 14.8 baud rate generator . chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 530 (3) csibn control register 2 (cbnctl2) cbnctl2 is an 8-bit register that controls the number of csibn serial transfer bits. this register can be read or written in 8-bit units. reset sets this register to 00h. caution the cbnctl2 register can be rewritten only when the cbnctl0.cbnpwr bit = 0 or when both the cbntxe and cbnrxe bits = 0. after reset: 00h r/w address: cb0ctl2 fffffd02h, cb1ctl2 fffffd12h, cb2ctl2 fffffd22h 0 cbnctl2 (n = 0 to 2) 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cbncl3 0 0 0 0 0 0 0 0 1 cbncl2 0 0 0 0 1 1 1 1 cbncl1 0 0 1 1 0 0 1 1 cbncl0 0 1 0 1 0 1 0 1 serial register bit length remarks 1. if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of the cbntx and cbnrx registers. 2. : don?t care chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 531 (a) transfer data length change function the csibn transfer data length can be set in 1-bit units between 8 and 16 bits using the cbnctl2.cbncl3 to cbnctl2.cbncl0 bits. when the transfer bit length is set to a value othe r than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of whether t he transfer start bit is the msb or lsb. any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. (i) transfer bit length = 10 bits, msb first 15 10 9 0 sobn sibn insertion of 0 (ii) transfer bit length = 12 bits, lsb first 0 sobn 11 12 15 sibn insertion of 0 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 532 (4) csibn status register (cbnstr) cbnstr is an 8-bit register t hat displays the csibn status. this register can be read or written in 8-bit or 1-bit units, but the cbntsf flag is read-only. reset sets this register to 00h. in addition to reset input, the cbnstr register can be initialized by clearing (0) the cbnctl0.cbnpwr bit. cbntsf communication stopped communicating cbntsf 0 1 communication status flag cbnstr (n = 0 to 2) 00 0 00 0 cbnove after reset 00h r/w address: cb0str fffffd03h, cb1str fffffd13h, cb2str fffffd23h during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock. no overrun overrun cbnove 0 1 overrun error flag an overrun error occurs when the next reception starts without reading the value of the receive buffer by cpu, upon completion of the receive operation. the cbnove flag displays the overrun error occurrence status in this case. the cbnove bit is valid also in the single transfer mode. therefore, when only using transmission, note the following. do not check the cbnove flag. read this bit even if reading the reception data is not required. the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 533 14.4 interrupt request signals csibn can generate the following two types of interrupt request signals. ? reception complete interrupt request signal (intcbnr) ? transmission enable interrupt request signal (intcbnt) of these two interrupt request signals, the reception comple te interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. table 14-2. interrupts and their default priority interrupt priority reception complete high transmission enable low (1) reception complete interrupt request signal (intcbnr) when receive data is transferred to the cbnrx register while reception is enabled, the reception complete interrupt request signal is generated. this interrupt request signal can also be generated if an overrun error occurs. when the reception complete interrupt request signal is acknowledged and the data is read, read the cbnstr register to check that the result of reception is not an error. in the single transfer mode, the intcbnr interrupt request signal is generated upon completion of transmission, even when only transmission is executed. (2) transmission enable interr upt request signal (intcbnt) in the continuous transmission or continuous transmi ssion/reception mode, transmit data is transferred from the cbntx register and, as soon as writing to cbntx has been enabled, the transmission enable interrupt request signal is generated. in the single transmission and single transmission/receptio n modes, the intcbnt interrupt is not generated. chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 534 14.5 operation 14.5.1 single transfer mode (master mode, transmission/reception mode) this section shows a case of msb first (cbnctl0.cbndir bit = 0), communication type 1 (see 14.3 (2) csibn control register 1 (cbnctl1) , and transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). cbntx write (55h) cbnrx read (aah) (aah) (55h) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (transmit data) sckbn pin cbntx register aah 00h cbnrx register shift register intcbnr signal note sibn pin sobn pin 0 0 0 1 0 0 1 0 1 1 cbntsf bit cbnsce bit (1) (5) (6) (8) (7) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of t he cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bi t, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the reception complete interrupt request signal (intcbnr) is output. (7) read the cbnrx register before clearing the cbnpwr bit to 0. (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop operation of csibn (end of transmission/reception). note in single transmission or single transmission/reception mode, the intcbnt signal is not generated. when communication is complete, the intcbnr signal is generated. remarks 1. the processing of steps (3) and (4) can be set simultaneously. 2. n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 535 14.5.2 single transfer mode (master mode, reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 1 (see 14.3 (2) csibn control register 1 (cbnctl1) , transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (aah) 1 0 1 1 00 1 01h 02h 05h 0ah 15h 2ah 55h aah 00h sckbn pin cbnrx register cbnrx read (dummy read) shift register cbnsce bit cbntsf bit intcbnr signal sibn pin sobn pin 0 l (1) (2) (3) (4) (5) (6) (7) (9) (8) cbnrx read (aah) aah 00h (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) set the cbnsce bit to 0 to set the final receive data status. (8) read the cbnrx register. (9) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the csibn operation (end of reception). remarks 1. the processing of steps (3) and (4) can be set simultaneously. 2. n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 536 14.5.3 continuous mode (master m ode, transmission/reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 3 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (7) (7) (6) (5) (1) (2) (3) (4) 96h 00h cch 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 55h cbntx register sckbn pin sobn pin sibn pin intcbnt signal intcbnr signal cbntsf bit cbnsce bit shift register so latch cbnrx register 0 0 0 0 aah 96h cch 1 1 1 0 0 0 1 01 0 0 (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of t he cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bi t, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the transmission enable interrupt request signal (int cbnt) is received and transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (8) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). in transmission mode or transmission/reception mode , the communication is not started by reading the cbnrx register. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 537 14.5.4 continuous mode (mast er mode, reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 2 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (6) (6) (7) (5) (1) (2) (3) (4) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn pin cbnsce bit sibn pin intcnr signal cbntsf bit shift register cbnrx register 1 1 0 55h aah aah 00h (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive da ta arrives or before the cbnpwr bit is cleared to 0. (7) set the cbnctl0.cbnsce bit = 0 while the last dat a being received to set the final receive data status. (8) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 538 14.5.5 continuous reception mode (error) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 2 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (9) (10) (7) (6) (5) aah 00h 1 0 0 0 0 0 01 1 1 1 1 sckbn pin sibn pin intcbnr signal cbntsf bit shift register cbnrx register cbnove bit 55h 55h 0 1 0 aah 1 (1) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) if the data could not be read befor e the end of the next transfer, the cbnstr.cbnove flag is set to 1 upon the end of reception and the intcbnr signal is output. (8) overrun error processing is performed after checki ng that the cbnove bit = 1 in the intcbnr interrupt servicing. (9) clear cbnove bit to 0. (10) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation csibn (end of reception). remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 539 14.5.6 continuous mode (slave m ode, transmission/reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 2 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.csncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (7) (7) (6) (5) 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx register sckbn pin sobn pin sibn pin intcbnt signal intcbnr signal shift register so latch cbnrx register 0 0 0 0 0 0 aah 96h cch 1 0 0 0 1 1 cbntsf bit cbnsce bit (1) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable supply of the csibn operation. (5) write the transfer data to the cbntx register. (6) the transmission enable interrupt request signal (int cbnt) is received and the transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register. (8) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat st eps (5) to (7) before (8). remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 540 14.5.7 continuous mode (s lave mode, reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 1 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (7) (6) (6) (5) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn pin sibn pin intcbnr signal cbntsf bit cbnsce bit shift register cbnrx register 1 1 55h aah 00h aah 0 (1) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register. when reading the last data, clear the cbnctl0.cbnsce bit to 0 before reading the cbnrx register. (7) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 541 14.5.8 clock timing (1/2) (1) communication type 1 (cbnckp = 0, cbndap = 0) d6 d5 d4 d3 d2 d1 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit d0 d7 (2) communication type 2 (cbnckp = 0, cbndap = 1) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. in the single transmission or single transmission/reception mode, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon completion of communication. 2. the intcbnr interrupt occurs if reception is co rrectly completed and receive data is ready in the cbnrx register while reception is enabled, and if an overrun error occurs. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon completion of communication. caution in communication type 2, the cbntsf bit is cleared half a sckbn clock after generation of an intcbnr interrupt request signal. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 542 (2/2) (3) communication type 3 (cbnckp = 1, cbndap = 0) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit (4) communication type 4 (cbnckp = 1, cbndap = 1) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. in the single transmission or single transmission/receptio n modes, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon completion of communication. 2. the intcbnr interrupt occurs if reception is co rrectly completed and receive data is ready in the cbnrx register while reception is enabled, and if an overrun error occurs. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon completion of communication. caution in communication type 4, the cbntsf bit is cleared half a sckbn clock after generation of an intcbnr interrupt request signal. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 543 14.6 output pin status with operation disabled (1) sckbn pin when csibn operation is disabled (cbnctl0.cbnpwr bit = 0), the sckbn pin output status is as follows. cbncks2 cbncks1 cbncks0 cbnckp sckbn pin output 1 1 1 high impedance 0 fixed to high level other than above 1 fixed to low level remarks 1. the output level of the sckbn pin changes if any of the cbnctl1.cbnckp and cbncks2 to cbncks0 bits is rewritten. 2. n = 0 to 2 3. : don?t care (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. cbntxe cbndap cbndir sobn pin output 0 fixed to low level 0 sobn latch value (low level) 0 cbntx register value (msb) 1 1 1 cbntx register value (lsb) remarks 1. the sobn pin output chan ges when any one of the cbnctl0.cbntxe, cbnctl0.cbndir bits, and cbnctl1.cbndap bit is rewritten. 2. n = 0 to 2 3. : don?t care chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 544 14.7 operation flow (1) single transmission start no yes intcbnr signal is generated? transfer data exists? end yes no initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register (start transfer). cbnpwr bit = 0 (cbnctl0) note set the cbnsce bit to 1 in the initial setting. caution in the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the cbntx register is written. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 545 (2) single reception start no intcbnr signal is generated? last data? end yes yes no initial setting (cbnctl0 note , cbnctl1 registers, etc.) cbnrx register dummy read (start reception) cbnsce bit = 0 (cbnctl0) cbnpwr bit = 0 (cbnctl0) cbnrx register read cbnrx register read note set the cbnsce bit to 1 in the initial setting. caution in the single mode, data cannot be correctly received if the next transfer clock is input earlier than the cbnrx register is read. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 546 (3) single transmission/reception start initial setting (cbnctl0 note 1 , cbnctl1 registers, etc.) write cbntx register (start transfer). end cbnpwr bit = 0, cbntxe bit = cbnrxe bit = 0 (cbnctl0) no transmission/reception transmission reception intcbnr signal is generated? yes transfer end? write cbntx register note 2 . read cbnrx register. read cbnrx register. no yes transfer end? write cbntx register note 2 . no yes transfer end? write cbntx register note 2 . no yes b b a a notes 1. set the cbnsce bit to 1 in the initial setting. 2. if the next transfer is reception only, dum my data is written to the cbntx register. caution even in the single mode, the cbnstr.cbnove flag is set to 1. if only transmission is used in the transmission/r eception mode, therefore, chec king the cbnove flag is not required. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 547 (4) continuous transmission start no yes intcbnt signal is generated? data to be transferred next exists? end yes no initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register (start transfer). cbnpwr bit = 0 (cbnctl0) no cbntsf bit = 1? (cbnstr) yes note set the cbnsce bit to 1 in the initial setting. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 548 (5) continuous reception start end no no yes intcbnr signal is generated? cbnove bit = 1? (cbnstr) no yes initial setting (cbnctl0 note , cbnctl1 registers, etc.) cbnrx register dummy read (start reception) cbnrx register read cbnrx register read cbnrx register read cbnrx register read yes is data being received last data? cbnsce bit = 0 (cbnctl0) cbnsce bit = 1 (cbnctl0) no intcbnr signal is generated ? yes cbnove bit clear (cbnstr) note set the cbnsce bit to 1 in the initial setting caution in the master mode, the clock is output wit hout limit when dummy da ta is read from the cbnrx register. to stop the cl ock, execute the flow marked in the above flowchart. in the slave mode, malfunction due to no ise during communication can be prevented by executing the flow marked in the above flowchart. before resuming communication, set the cbn ctl0.cbnsce bit to 1, and read dummy data from the cbnrx register. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 549 (6) continuous transmission/reception start end no no intcbnr signal is generated? yes no intcbnt signal is generated ? yes initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register. cbnrx register read yes yes is data completely received last data? no write cbntx register. yes is data being transferred last data? no cbnove bit = 0? (cbnstr) cbnove bit clear (cbnstr) note set the cbnsce bit to 1 in the initial setting. remark n = 0 to 2 chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 550 14.8 baud rate generator the clock generated by the baud rate generator (pre scaler 3) is supplied to the watch timer and csib0. (1) prescaler mode register 0 (prsm0) the prsm0 register controls generati on of the baud rate signal for csib. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled enabled bgce0 0 1 baud rate output f x f x /2 f x /4 f x /8 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 count clock selection (f bgcs ) after reset: 00h r/w address: fffff8b0h 5 mhz 200 ns 400 ns 800 ns 1.6 s cautions 1. do not rewrite the prsm0 register while watch timer and csib0 are operating. 2. set the prsm0 register befo re setting the bgce0 bit to 1. chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 551 (2) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare registers. this register can be read or written in 8-bit units. reset sets this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 register while watch timer and csib are operating. 2. set the prscm0 register before setting the prsm0.bgce0 bit to 1. 14.8.1 baud rate generation the transmission/reception clock is generated by dividing the main clock. the baud rate generated from the main clock is obtained by the following equation. f brg = remark f brg : brg count clock f xx : main clock oscillation frequency k: prsm0 register setting value = 0 to 3 n: prscm0 register setting value = 1 to 256 however, n = 256 only when prscm0 register is set to 00h. f xx 2 k+1 n chapter 14 3-wire variable-length serial i/o (csib) preliminary user?s manual u17717ej2v0ud 552 14.9 cautions (1) when transferring transmit data and receive data using dma transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. check that the no overrun error has occurred by reading the cbnstr.cbnove bit after dma transfer has been completed. (2) in regards to registers that are forbidden from bei ng rewritten during operations (cbnctl0.cbnpwr bit is 1), if rewriting has been carried out by mistake during oper ations, set the cbnctl0.cbnpwr bit to 0 once, then initialize csibn. registers to which rewriting during op eration are prohibited are shown below. ? cbnctl0 register: cbntxe, cbnrxe, cbndir, cbntms bits ? cbnctl1 register: cbnckp, cbndap, cbncks2 to cbncks0 bits ? cbnctl2 register: cbncl3 to cbncl0 bits (3) in communication type 2 and 4 (cbnctl1.cbndap bit = 1), the cbnstr.cbntsf bit is cleared half a sckbn clock after occurrence of a reception complete interrupt (intcbnr). in the single transfer mode, writing the next transmit data is ignored during communication (cbntsf bit = 1), and the next communication is not st arted. also if reception-only co mmunication (cbnctl0.cbntxe bit = 0, cbnctl0.cbnrxe bit = 1) is set, the next communication is not started even if the receive data is read during communication (cbntsf bit = 1). therefore, when using the single transfer mode with communication type 2 or 4 (cbndap bit = 1), pay particular attention to the following. ? to start the next transmission, confirm that cbntsf bit = 0 and then write the transmit data to the cbntx register. ? to perform the next reception continuously when re ception-only communication (cbntxe bit = 0, cbnrxe bit = 1) is set, confirm that cbntsf bit = 0 and then read the cbnrx register. or, use the continuous transfer mode inst ead of the single transfer mode. us e of the continuous transfer mode is recommended especially for using dma. remark n = 0 to 2 preliminary user?s manual u17717ej2v0ud 553 chapter 15 dma function (dma controller) the v850es/hj2 includes a direct memory access (dma) controller (dmac) that ex ecutes and controls dma transfer. the dmac controls data transfer between memory and i/o, between memo ries, or between i/os based on dma requests issued by the on-chip peripheral i/o (serial in terface, timer/counter, and a/d converter), interrupts from external input pins, or software triggers (memory refers to internal ram or external memory). 15.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? transfer type: two-cycle transfer ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (seria l interface, timer/counter, a/d converter) or interrupts from external input pin ? requests by software trigger ? transfer targets ? internal ram ? peripheral i/o ? peripheral i/o ? peripheral i/o ? internal ram ? external memory ? external memory ? peripheral i/o ? external memory ? external memory chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 554 15.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/hj2 bus interface external bus external ram external rom external i/o dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) remark n = 0 to 3 chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 555 15.3 registers (1) dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma source addresse s (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer source set the address (a25 to a16) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa25 to sa16 set the address (a15 to a0) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa15 to sa0 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah, dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h dsanl (n = 0 to 3) sa15 sa14 sa13 sa12 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa7 sa8 sa9 sa10 sa11 dsanh (n = 0 to 3) ir 000 sa22 sa21 sa20 sa19 sa18 sa17 sa16 sa23 sa24 sa25 0 0 cautions 1. be sure to clear bits 14 to 10 of the dsanh register to 0. 2. set the dsanh and dsanl re gisters at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the dsan register is read, two 16-bit re gisters, dsanh and dsanl, are read. if reading and updating conflict, the value being updated may be read (see 15.13 cautions). 4. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 556 (2) dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma destination addre ss (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, ddanh and ddanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer destination set an address (a25 to a16) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da25 to da16 set an address (a15 to a0) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da15 to da0 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, dda2h fffff096h, dda3h fffff09eh, dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch ddanl (n = 0 to 3) da15 da14 da13 da12 da6 da5 da4 da3 da2 da1 da0 da7 da8 da9 da10 da11 ddanh (n = 0 to 3) ir 000 da22 da21 da20 da19 da18 da17 da16 da23 da24 da25 0 0 cautions 1. be sure to clear bits 14 to 10 of the ddanh register to 0. 2. set the ddanh and ddanl registers at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the ddan register is read, two 16-bit registers, ddanh and ddanl, are read. if reading and updating conflict, a va lue being updated may be read (see 15.13 cautions). 4. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 557 (3) dma byte count registers 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the byte transfer c ount for dma channel n (n = 0 to 3). these registers hold the remaining tr ansfer count during dma transfer. these registers are decremented by 1 per one transfer regardless of the trans fer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. these registers can be read or written in 16-bit units. byte transfer count 1 or remaining byte transfer count byte transfer count 2 or remaining byte transfer count : byte transfer count 65,536 (2 16 ) or remaining byte transfer count bc15 to bc0 0000h 0001h : ffffh byte transfer count setting or remaining byte transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h dbcn (n = 0 to 3) 15 bc15 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 the number of transfer data set first is held when dma transfer is complete. cautions 1. set the dbcn register at the follow ing timing when dma transf er is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 558 (4) dma addressing control registers 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-bit registers that control the dma transfer mode for dma channel n (n = 0 to 3). these registers can be read or written in 16-bit units. reset sets these registers to 0000h. dadcn (n = 0 to 3) 8 bits 16 bits ds0 0 1 setting of transfer data size increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of the transfer source address increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of the destination address after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sad1 sad0 dad1 dad0 0 0 0 0 0ds000 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 cautions 1. be sure to clear bits 15, 13 to 8, and 3 to 0 of the dadcn register to ?0?. 2. set the dadcn register at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. the ds0 bit specifies the size of the transfer data, and does not control bus sizing. if 8-bit data (ds0 bit = 0) is set, therefore, the lower data bus is not always used. 4. if the transfer data size is set to 16 bits (ds0 bit = 1), transfer cannot be started from an odd address. transfer is always started from an address with the first bit of the lower address aligned to 0. 5. if dma transfer is executed on an on-chip peripheral i/o register (as the transfer source or destination), be sure to specify the same transfer size as the re gister size. for example, to execute dma transfer on an 8-bit register , be sure to specify 8-bit transfer. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 559 (5) dma channel control registers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bit registers t hat control the dma transfer operating mode for dma channel n. these registers can be read or written in 8-bit or 1-bit units. (however, bit 7 is read-only and bits 1 and 2 are write-only. if bit 1 or 2 is read, the read value is always 0.) reset sets these registers to 00h. dchcn (n = 0 to 3) dma transfer had not completed. dma transfer had completed. it is set to 1 on the last dma transfer and cleared to 0 when it is read. tcn note 1 0 1 status flag indicates whether dma transfer through dma channel n has completed or not dma transfer disabled dma transfer enabled dma transfer is enabled when the enn bit is set to 1. when dma transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. to abort dma transfer, clear the enn bit to 0 by software. to resume, set the enn bit to 1 again. when aborting or resuming dma transfer, however, be sure to observe the procedure described in 15.13 cautions . enn 0 1 setting of whether dma transfer through dma channel n is to be enabled or disabled this is a software startup trigger of dma transfer. if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn note 2 after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn note 2 enn 0 1 2 3 4 5 6 7 initn note 2 if the initn bit is set to 1 with dma transfer disabled (enn bit = 0), the dma transfer status can be initialized. when re-setting the dma transfer status (re-setting the ddanh, ddanl, dsanh, dsanl, dbcn, and dadcn registers) before dma transfer is completed (before the tcn bit is set to 1), be sure to initialize the dma channel. when initializing the dma controller, however, be sure to observe the procedure described in 15.13 cautions . notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. cautions 1. be sure to clear bits 6 to 3 of the dchcn register to ?0?. 2. when dma transfer is completed (when a terminal count is generated), the enn bit is cleared to 0 and then the tcn bit is set to 1. if the dchcn regist er is read while its bits are being updated, a value indicating ?transfer not co mpleted and transfer is disabled? (tcn bit = 0 and enn bit = 0) may be read. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 560 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that control the dma transfer start trigger via interrupt request signals from on-chip peripheral i/o. the interrupt request signals set by these re gisters serve as dma transfer start factors. these registers can be read or written in 8-bit units. however, dfn bit can be read or written in 1-bit units. reset sets these registers to 00h. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 dma transfer request flag after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 7 note the dfn bit is a write-only bit. write 0 to this bi t to clear a dma transfer request if an interrupt that is specified as the cause of starting dma trans fer occurs while dma transfer is disabled. cautions 1. set the ifcn5 to if cn0 bits at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. an interrupt request that is generated in the standby mode (idel1, idle2, stop, or sub- idle mode) does not start the dma transfer cycle (nor is the dfn bit set to 1). 3. if a dma start factor is selected by the ifcn 5 to ifcn0 bits, the dfn bi t is set to 1 when an interrupt occurs from the selected on-chip pe ripheral i/o, regardless of whether the dma transfer is enabled or disable d. if dma is enabled in this status, dma transfer is immediately started. remark for the ifcn5 to ifcn0 bits, see table 15-1 dma start factors . chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 561 table 15-1. dma start factors (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 0 0 0 0 0 1 intlvi 0 0 0 0 1 0 intp0 0 0 0 0 1 1 intp1 0 0 0 1 0 0 intp2 0 0 0 1 0 1 intp3 0 0 0 1 1 0 intp4 0 0 0 1 1 1 intp5 0 0 1 0 0 0 intp6 0 0 1 0 0 1 intp7 0 0 1 0 1 0 inttq0ov 0 0 1 0 1 1 inttq0cc0 0 0 1 1 0 0 inttq0cc1 0 0 1 1 0 1 inttq0cc2 0 0 1 1 1 0 inttq0cc3 0 0 1 1 1 1 inttp0ov 0 1 0 0 0 0 inttp0cc0 0 1 0 0 0 1 inttp0cc1 0 1 0 0 1 0 inttp1ov 0 1 0 0 1 1 inttp1cc0 0 1 0 1 0 0 inttp1cc1 0 1 0 1 0 1 inttp2ov 0 1 0 1 1 0 inttp2cc0 0 1 0 1 1 1 inttp2cc1 0 1 1 0 0 0 inttp3ov 0 1 1 0 0 1 inttp3cc0 0 1 1 0 1 0 inttp3cc1 0 1 1 0 1 1 inttm0eq0 0 1 1 1 0 0 intcb0r 0 1 1 1 0 1 intcb0t 0 1 1 1 1 0 intcb1r 0 1 1 1 1 1 intcb1t 1 0 0 0 0 0 intua0r 1 0 0 0 0 1 intua0t 1 0 0 0 1 0 intua1r 1 0 0 0 1 1 intua1t 1 0 0 1 0 0 intad 1 0 1 0 0 1 intkr 1 0 1 0 1 0 inttq1ov remark n = 0 to 3 chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 562 table 15-1. dma start factors (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 1 0 1 1 inttq1cc0 1 0 1 1 0 0 inttq1cc1 1 0 1 1 0 1 inttq1cc2 1 0 1 1 1 0 inttq1cc3 1 0 1 1 1 1 intua2r 1 1 0 0 0 0 intua2t 1 1 0 1 0 1 inttq2ov 1 1 0 1 1 0 inttq2cc0 1 1 0 1 1 1 inttq2cc1 1 1 1 0 0 0 inttq2cc2 1 1 1 0 0 1 inttq2cc3 1 1 1 0 1 0 intcb2r 1 1 1 0 1 1 intcb2t remark n = 0 to 3 chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 563 15.4 transfer targets table 15-2 shows the relationship between the transfer targets ( : transfer enabled, : transfer disabled). table 15-2. relationship between transfer targets transfer destination internal rom on-chip peripheral i/o internal ram external memory on-chip peripheral i/o internal ram external memory source internal rom caution the operation is not guaranteed for combinat ions of transfer destination and source marked with ? ? in table 15-2. 15.5 transfer modes single transfer is supported as the transfer mode. in single transfer mode, the bus is released at each byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher priority dma transfer r equest is issued, the higher priority dma request always takes precedence. if a new transfer request of the same channel and a transfer request of another channel with a lower priority are generated in a transfer cycle, dma transfer of the channel with t he lower priority is executed after the bus is released to the cpu (the new transfer request of the same channel is ignored in the transfer cycle). chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 564 15.6 transfer types as a transfer type, the 2-cycle transfer is supported. in two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. in the read cycle, the transfer source address is output and reading is performed from the source to the dmac. in the write cycle, the transfer destination addr ess is output and writing is performed from the dmac to the destination. an idle cycle of one clock is always inserted between a read cycle and a write cycle. if the data bus width differs between the transfer source and destination for dma transfe r of two cycles, the operation is performed as follows. <16-bit data transfer> <1> transfer from 32-bit bus 16-bit bus a read cycle (the higher 16 bits are in a high-impedan ce state) is generated, followed by generation of a write cycle (16 bits). <2> transfer from 16-/32-bit bus to 8-bit bus a 16-bit read cycle is generated once, and t hen an 8-bit write cycle is generated twice. <3> transfer from 8-bit bus to 16-/32-bit bus an 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> transfer between 16-bit bus and 32-bit bus a 16-bit read cycle is generated once, and t hen a 16-bit write cycle is generated once. for dma transfer executed to an on-chip peripheral i/o register (tr ansfer source/destination), be sure to specify the same transfer size as the register size. for example, for dma transfer to an 8-bit register, be sure to specify byte (8- bit) transfer. remark the bus width of each transfer target (tr ansfer source/destination) is as follows. ? on-chip peripheral i/o: 16-bit bus width ? internal ram: 32-bit bus width ? external memory: 8-bit or 16-bit bus width chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 565 15.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 the priorities are checked for every transfer cycle. 15.8 time related to dma transfer the time required to respond to a dma request, and the minimum number of clocks required for dma transfer are shown below. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note 1 + transfer destination memory access (<2>) dma cycle minimum number of execution clocks <1> dma request response time 4 clocks (min.) + noise elimination time note 2 external memory access depends on connected memory. internal ram access 2 clocks note 3 <2> memory access peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register note 4 notes 1. one clock is always inserted between a read cycle and a write cycle in dma transfer. 2. if an external interrupt (intpn) is specified as the tr igger to start dma transfer, noise elimination time is added (n = 0 to 14). 3. two clocks are required for a dma cycle. 4. more wait cycles are necessary for accessing a specific peripheral i/o register (for details, see 3.4.8 (2) ). chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 566 15.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. (1) request by software if the stgn bit is set to 1 while the dchcn.tcn bit = 1 and enn bit = 1 (dma transfer enabled), dma transfer is started. to request the next dma transfer cycle immediately after that, confirm, by using th e dbcn register, that the preceding dma transfer cycle has been completed, and set the stgn bit to 1 again (n = 0 to 3). tcn bit = 0, enn bit = 1 stgn bit = 1 ? starts the first dma transfer. confirm that the contents of the dbcn register have been updated. stgn bit = 1 ? starts the second dma transfer. : generation of terminal count ? enn bit = 0, tc n bit = 1, and intdman signal is generated. (2) request by on-chip peripheral i/o if an interrupt request is generated from the on-chip peripheral i/o set by the dtfrn register when the dchcn.tcn bit = 0 and enn bit = 1 (dma transf er enabled), dma transfer is started. cautions 1. two start factors (software trigger a nd hardware trigger) cannot be used for one dma channel. if two start factors are simultane ously generated for one dma channel, only one of them is valid. the start factor that is valid cannot be identified. 2. a new transfer request that is generate d after the preceding dma transfer request was generated or in the preceding dma tran sfer cycle is ignored (cleared). 3. the transfer request interval of the sam e dma channel varies depending on the setting of bus wait in the dma transfer cycle, the start status of the other channels, or the external bus hold request. in particular, as described in caution 2, a new transfer request that is generated for the same channel before the dma transfer cycle or during the dma transfer cycle is ignored. therefore, the transfer re quest intervals for the same dma channel must be sufficiently separated by th e system. when the software tr igger is used, completion of the dma transfer cycle that was generated before can be checked by updating the dbcn register. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 567 15.10 dma abort factors dma transfer is aborted if a bus hold occurs. the same applies if transfer is ex ecuted between the intern al memory/on-chip peripheral i/o and internal memory/on-chip peripheral i/o. when the bus hold is cleared, dma transfer is resumed. 15.11 end of dma transfer when dma transfer has been completed the number of ti mes set to the dbcn register and when the dchcn.enn bit is cleared to 0 and tcn bit is set to 1, a dma transfer end interrupt request signal (intdman) is generated for the interrupt controller (intc) (n = 0 to 3). the v850es/hj2 does not output a terminal count signal to an external device. therefore, confirm completion of dma transfer by using the dma transfer end interrupt or polling the tcn bit. 15.12 operation timing figures 15-1 to 15-4 show dma operation timing. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 568 figure 15-1. priority of dma (1) preparation for transfer read write idle end processing dma2 processing cpu processing dma1 processing cpu processing cpu processing dma0 processing dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit preparation for transfer read write idle end processing preparation for transfer read remarks 1. transfer in the order of dma0 dma1 dma2 2. in the case of transfer between external memory spaces (multiplexed bus, no wait) chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 569 figure 15-2. priority of dma (2) preparation for transfer read write idle dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing read write idle end processing read preparation for transfer preparation for transfer end processing remarks 1. transfer in the order of dma0 dma1 dma0 (dma2 is held pending.) 2. in the case of transfer between external memory spaces (multiplexed bus, no wait) chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 570 figure 15-3. period in which dma transfer request is ignored (1) preparation for transfer read cycle write cycle idle end processing dma transfer mode of processing dfn bit system clock transfer request generated after this can be acknowledged dma0 processing cpu processing cpu processing note 2 note 2 dman transfer request note 1 note 2 notes 1. interrupt from on-chip peripheral i/o , or software trigger (stgn bit) 2. new dma request of the same channel is ignor ed between when the first request is generated and the end processing is complete. remark in the case of transfer between external memory spaces (multiplexed bus, no wait) chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 571 figure 15-4. period in which dma transfer request is ignored (2) preparation for transfer read write idle <1> <2> <3> <4> cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit preparation for transfer read write idle preparation for transfer read end processing end processing <1> dma0 transfer request <2> new dma0 transfer request is generated during dma0 transfer. a dma transfer request of the same channel is ignored during dma transfer. <3> requests for dma0 and dma1 are generated at the same time. dma0 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma1 request is acknowledged. <4> requests for dma0, dma1, and dma2 are generated at the same time. dma1 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma0 request is acknowledged according to priority. dma2 request is held pending (transfer of dma2 occurs next). chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 572 15.13 cautions (1) caution for vswc register when using the dmac, be sure to set an appropriate val ue, in accordance with the operating frequency, to the vswc register. when the default value (77h) of the vsw c register is used, or if an inappr opriate value is set to the vswc register, the operation is not correctly perfo rmed (for details of the vswc register, see 3.4.8 (1) (a) system wait control register (vswc) ). (2) caution for dma transfer executed on internal ram when executing the following instructions located in th e internal ram, do not ex ecute a dma transfer that transfers data to/from the internal ram (transfer source/destination), because the cpu may not operate correctly afterward. ? data access instruction to misaligned address located in internal ram conversely, when executing a dma transfer to tran sfer data to/from the in ternal ram (transfer source/destination), do not execut e the above two instructions. (3) caution for reading dchcn .tcn bit (n = 0 to 3) the tcn bit is cleared to 0 when it is read, but it is not automat ically cleared even if it is read at a specific timing. to accurately clear the tcn bit, add the following processing. (a) when waiting for completion of dma transfer by polling tcn bit confirm that the tcn bit has been set to 1 (after tcn bit = 1 is read), and then read the tcn bit three more times. (b) when reading tcn bit in interrupt servicing routine execute reading the tcn bit three times. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 573 (4) dma transfer initialization pro cedure (setting dchcn.initn bit to 1) even if the initn bit is set to 1 when the channel exec uting dma transfer is to be initialized, the channel may not be initialized. to accurately initialize the c hannel, execute either of the following two procedures. (a) temporarily stop transfer of all dma channels initialize the channel executing dma transfer using the procedure in <1> to <7> below. note, however, that tcn bit is cleared to 0 when st ep <5> is executed. make sure that the other processing programs do not expect that the tcn bit is 1. <1> disable interrupts (di). <2> read the dchcn.enn bit of dm a channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> clear the enn bit of the dma channels used (including the channel to be forcibly terminated) to 0. to clear the enn bit of the last dma channel, execute th e clear instruction twice. if the target of dma transfer (transfer source/destination) is the inte rnal ram, execute the instruction three times. example: execute instructions in t he following order if channels 0, 1, and 2 are used (if the target of transfer is not the internal ram). ? clear dchc0.e00 bit to 0. ? clear dchc1.e11 bit to 0. ? clear dchc2.e22 bit to 0. ? clear dchc2.e22 bit to 0 again. <4> set the initn bit of the channel to be forcibly terminated to 1. <5> read the tcn bit of each channel not to be forcib ly terminated. if both the tcn bit and the enn bit read in <2> are 1 (logical product (and) is 1), clear the saved enn bit to 0. <6> after the operation in <5>, write the enn bit value to the dchcn register. <7> enable interrupts (ei). caution be sure to execute step <5> above to pr event illegal setting of the enn bit of the channels whose dma transfer has been normall y completed between <2> and <3>. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 574 (b) repeatedly execute setting initn bit until transfer is forcibly terminated correctly <1> suppress a request from the dma request source of the channel to be forcibly terminated (stop operation of the on-ch ip peripheral i/o). <2> check that the dma transfer request of the channel to be forcibly terminated is not held pending, by using the dtfrn.dfn bit. if a dma transfer reques t is held pending, wait until execution of the pending request is completed. <3> when it has been confirmed that t he dma request of the channel to be fo rcibly terminated is not held pending, clear the enn bit to 0. <4> again, clear the enn bit of the channel to be forcibly terminated. if the target of transfer for the channel to be forc ibly terminated (transfer source/destination) is the internal ram, execute th is operation once more. <5> copy the initial number of trans fers of the channel to be forcibly terminated to a general-purpose register. <6> set the initn bit of the channel to be forcibly terminated to 1. <7> read the value of the dbcn regist er of the channel to be forcibly terminated, and compare it with the value copied in <5>. if the two values do not match, repeat operations <6> and <7>. remarks 1. when the value of the dbcn regist er is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. if not, the remaining number of transfers is read. 2. note that method (b) may take a long time if the application frequently uses dma transfer for a channel other than the dma channel to be forcibly terminated. (5) procedure of temporarily stoppi ng dma transfer (clearing enn bit) stop and resume the dma transfer under ex ecution using the following procedure. <1> suppress a transfer request from the dma request s ource (stop the operation of the on-chip peripheral i/o). <2> check the dma transfer request is not held pending , by using the dfn bit (check if the dfn bit = 0). if a request is pending, wait until execution of the pending dma transfer request is completed. <3> if it has been confirmed that no dma transfer requ est is held pending, clear the enn bit to 0 (this operation stops dma transfer). <4> set the enn bit to 1 to resume dma transfer. <5> resume the operation of the dma request source that has been stopped (start the operation of the on- chip peripheral i/o). (6) memory boundary the operation is not guaranteed if th e address of the transfer source or destination exceeds the area of the dma target (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (7) transferring misaligned data dma transfer of misaligned data with a 16-bit bus width is not supported. if an odd address is specified as the trans fer source or destination, the leas t significant bit of the address is forcibly assumed to be 0. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 575 (8) bus arbitration for cpu because the dma controller has a higher priority bus ma stership than the cpu, a cpu access that takes place during dma transfer is held pending unt il the dma transfer cycle is complete d and the bus is released to the cpu. however, the cpu can access the external memory, on- chip peripheral i/o, and inte rnal ram to/from which dma transfer is not being executed. ? the cpu can access the internal ram when dma trans fer is being executed between the external memory and on-chip peripheral i/o. ? the cpu can access the internal ram and on-chip peripheral i/o wh en dma transfer is being executed between the external memory and external memory. (9) registers/bits that must not be rewritten during dma operation set the following registers at the following ti ming when a dma operation is not under execution. [registers] ? dsanh, dsanl, ddanh, ddanl, dbcn, and dadcn registers ? dtfrn.ifcn5 to dtfrn.ifcn0 bits [timing of setting] ? period from after reset to start of the first dma transfer ? time after channel initializ ation to start of dma transfer ? period from after completion of dma transfer (tcn bit = 1) to start of the next dma transfer (10) be sure to set the foll owing register bits to 0. ? bits 14 to 10 of dsanh register ? bits 14 to 10 of ddanh register ? bits 15, 13 to 8, and 3 to 0 of dadcn register ? bits 6 to 3 of dchcn register (11) dma start factor do not start two or more dma channels with the same st art factor. if two or more channels are started with the same factor, a dma channel with a lower priority may be acknowledged earlier than a dma channel with a higher priority. chapter 15 dma function (dma controller) preliminary user?s manual u17717ej2v0ud 576 (12) read values of dsan and ddan registers values in the middle of updating may be read from t he dsan and ddan registers during dma transfer (n = 0 to 3). for example, if the dsanh regist er and then the dsanl register ar e read when the dma transfer source address (dsan register) is 0000ffffh and the count direction is incremental (dadcn.sad1 and dadcn.sad0 bits = 00), the value of the dsan regist er differs as follows, depending on whether dma transfer is executed immediately after the dsanh register is read. (a) if dma transfer does not occu r while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> read value of dsanl register: dsanl = ffffh (b) if dma transfer occurs while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan = 00100000h <4> read value of dsanl register: dsanl = 0000h preliminary user?s manual u17717ej2v0ud 577 chapter 16 interrupt/except ion processing function the v850es/hj2 is provided with a dedicated interrupt cont roller (intc) for interrupt servicing and can process a total of 66/68 interrupt requests. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/hj2 can process interrupt request signals from the on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 16.1 features interrupts non-maskable interrupts: 2 sources maskable interrupts: external: 15, internal: 49/51 sources (see table 1-1 ) 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for eac h maskable interrupt request. noise elimination, edge detection, and valid edge specification for external interrupt request signals. exceptions software exceptions: 32 sources exception trap: 2 sources (illegal opcode exception, debug trap) interrupt/exception sources are listed in table 16-1. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 578 table 16-1. interrupt source list (1/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset interrupt ? reset reset pin input reset input by internal source reset 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt2 wdt2 overflow wdt2 0020h 00000020h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/ dbtrap instruction ? 0060h 00000060h nextpc ? 0 intlvi low voltage detection poclvi 0080h 00000080h nextpc lviic 1 intp0 external interrupt pin input edge detection (intp0) pin 0090h 00000090h nextpc pic0 2 intp1 external interrupt pin input edge detection (intp1) pin 00a0h 000000a0h nextpc pic1 3 intp2 external interrupt pin input edge detection (intp2) pin 00b0h 000000b0h nextpc pic2 4 intp3 external interrupt pin input edge detection (intp3) pin 00c0h 000000c0h nextpc pic3 5 intp4 external interrupt pin input edge detection (intp4) pin 00d0h 000000d0h nextpc pic4 6 intp5 external interrupt pin input edge detection (intp5) pin 00e0h 000000e0h nextpc pic5 7 intp6 external interrupt pin input edge detection (intp6) pin 00f0h 000000f0h nextpc pic6 8 intp7 external interrupt pin input edge detection (intp7) pin 0100h 00000100h nextpc pic7 9 inttq0ov tmq0 overflow tmq0 0110h 00000110h nextpc tq0ovic 10 inttq0cc0 tmq0 capture 0/compare 0 match tmq0 0120h 00000120h nextpc tq0ccic0 11 inttq0cc1 tmq0 capture 1/compare 1 match tmq0 0130h 00000130h nextpc tq0ccic1 12 inttq0cc2 tmq0 capture 2/compare 2 match tmq0 0140h 00000140h nextpc tq0ccic2 13 inttq0cc3 tmq0 capture 3/compare 3 match tmq0 0150h 00000150h nextpc tq0ccic3 14 inttp0ov tmp0 overflow tmp0 0160h 00000160h nextpc tp0ovic 15 inttp0cc0 tmp0 capture 0/compare 0 match tmp0 0170h 00000170h nextpc tp0ccic0 16 inttp0cc1 tmp0 capture 1/compare 1 match tmp0 0180h 00000180h nextpc tp0ccic1 17 inttp1ov tmp1 overflow tmp1 0190h 00000190h nextpc tp1ovic 18 inttp1cc0 tmp1 capture 0/compare 0 match tmp1 01a0h 000001ah nextpc tp1ccic0 19 inttp1cc1 tmp1 capture 1/compare 1 match tmp1 01b0h 000001b0h nextpc tp1ccic1 20 inttp2ov tmp2 overflow tmp2 01c0h 000001c0h nextpc tp2ovic maskable interrupt 21 inttp2cc0 tmp2 capture 0/compare 0 match tmp2 01d0h 000001d0h nextpc tp2ccic0 notes 1. for the restoring in the case of intwdt2, see 16.2.2 (2) from intwdt2 signal . 2. n = 0h to fh chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 579 table 16-1. interrupt source list (2/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 22 inttp2cc1 tmp2 capture 1/compare 1 match tmp2 01e0h 000001e0h nextpc tp2ccic1 23 inttp3ov tmp3 overflow tmp3 01f0h 000001f0h nextpc tp3ovic 24 inttp3cc0 tmp3 capture 0/compare 0 match tmp3 0200h 00000200h nextpc tp3ccic0 25 inttp3cc1 tmp3 capture 1/compare 1 match tmp3 0210h 00000210h nextpc tp3ccic1 26 inttm0eq0 tmm0 compare match tmm0 0220h 00000220h nextpc tm0eqic0 27 intcb0r csib0 reception completi on csib0 0230h 00000230h nextpc cb0ric 28 intcb0t csib0 consecutive transmission write enable csib0 0240h 00000240h nextpc cb0tic 29 intcb1r csib1 reception completi on csib1 0250h 00000250h nextpc cb1ric 30 intcb1t csib1 consecutive transmission write enable csib1 0260h 00000260h nextpc cb1tic 31 intua0r uarta0 reception completion uarta0 0270h 00000280h nextpc ua0ric 32 intua0t uarta0 transmission enabl e uarta0 0280h 00000280h nextpc ua0tic 33 intua1r uarta1 reception completion/uarta1 reception error uarta1 0290h 00000290h nextpc ua1ric 34 intua1t uarta1 transmission enable u arta1 02a0h 000002a0h nextpc ua1tic 35 intad a/d conversion completi on a/d 02bh 000002b0h nextpc adic 36 intkr key return interrupt request kr 0300h 00000300h nextpc kric 37 intwti watch timer interv al wt 0310h 00000310h nextpc wtiic 38 intwt watch timer reference time wt 0320h 00000320h nextpc wtic 39 intp8 external interrupt pin input edge detection (intp8) pin 0330h 00000330h nextpc pic8 40 intp9 external interrupt pin input edge detection (intp9) pin 0340h 00000340h nextpc pic9 41 intp10 external interrupt pin input edge detection (intp10) pin 0350h 00000350h nextpc pic10 42 inttq1ov tmq1 overflow tm q1 0360h 00000360h nextpc tq1ovic 43 inttq1cc0 tmq1 capture 0/compare 0 match tmq1 0370h 00000370h nextpc tq1ccic0 44 inttq1cc1 tmq1 capture 1/compare 1 match tmq1 0380h 00000380h nextpc tq1ccic1 45 inttq1cc2 tmq1 capture 2/compare 2 match tmq1 0390h 00000390h nextpc tq1ccic2 46 inttq1cc3 tmq1 capture 3/compare 3 match tmq1 03a0h 000003a0h nextpc tq1ccic3 47 intua2r uarta2 reception completion/error uarta2 03b0h 000003b0h nextpc ua2ric 48 intua2t uarta2 transmission enable uarta2 03c0h 000003c0h nextpc ua2tic 49 intdma0 dma0 transfer end dma 0410h 00000410h nextpc dmaic0 50 intdma1 dma1 transfer end dma 0420h 00000420h nextpc dmaic1 51 intdma2 dma2 transfer end dma 0430h 00000430h nextpc dmaic2 maskable interrupt 52 intdma3 dma3 transfer end dma 0440h 00000440h nextpc dmaic3 chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 580 table 16-1. interrupt source list (3/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 53 intp11 external interrupt pin input edge detection (intp11) pin 0450h 00000450h nextpc pic11 54 intp12 external interrupt pin input edge detection (intp12) pin 0460h 00000460h nextpc pic12 55 intp13 external interrupt pin input edge detection (intp13) pin 0470h 00000470h nextpc pic13 56 intp14 external interrupt pin input edge detection (intp14) pin 0480h 00000480h nextpc pic14 57 inttq2ov tmq2 overflow tm q2 0490h 00000490h nextpc tq2ovic 58 inttq2cc0 tmq2 capture 0/compare 0 match tmq2 04a0h 000004a0h nextpc tq2ccic0 59 inttq2cc1 tmq2 capture 1/compare 1 match tmq2 04b0h 000004b0h nextpc tq2ccic1 60 inttq2cc2 tmq2 capture 2/compare 2 match tmq2 04c0h 000004c0h nextpc tq2ccic2 61 inttq2cc3 tmq2 capture 3/compare 3 match tmq2 04d0h 000004d0h nextpc tq2ccic3 62 intcb2r csib2 reception completion/error csib2 04e0h 000004e0h nextpc cb2ric 63 intcb2t csib2 continuous transmission write enable csib2 04f0h 000004f0h nextpc cb2tic 64 intua3r note uarta3 reception completion/error uarta3 0500h 00000500h nextpc ua3ric maskable interrupt 65 intua3t note uarta3 transmission enable uart a3 0510h 00000510h nextpc ua3tic note pd70f3711, 70f3712 only remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. the priority order of non-maskable interrupt is intwdt2 > nmi. restored pc: the value of the program count er (pc) saved to eipc, fepc, or dbpc when interrupt servicing is started. note, however, that the restored pc when a non- maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the proc essing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 581 16.2 non-maskable interrupts a non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupt request signals. this product has the following two non-maskable interrupt request signals. ? nmi pin input (nmi) ? non-maskable interrupt request signal generated by overflow of watchdog timer (intwdt2) the valid edge of the nmi pin can be selected from four types: ?rising edge? , ?falling edge?, ?both edges?, and ?no edge detection?. the function of the nmi pin is enabled by setting t he pmc0.pmc02 bit to 1 and the intf0.intf02 bit and intr0.intr02 bit to a desired value, and specifying a desired valid edge. the non-maskable interrupt request signal generated by over flow of watchdog timer 2 (intwdt2) functions when the wdtm2.wdm21 and wdtm2.wdm20 bits are set to ?01?. if two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt reques t signal with the lower priority is ignored). intwdt2 > nmi if a new nmi or intwdt2 request signal is issued while an nmi is being serviced, it is serviced as follows. (1) if new nmi request signal is i ssued while nmi is being serviced the new nmi request signal is held pending, regardle ss of the value of the psw.np bit. the pending nmi request signal is acknowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). (2) if intwdt2 request signal is issued while nmi is being serviced the intwdt2 request signal is held pending if the np bit remains set (1) while the nmi is being serviced. the pending intwdt2 request signal is acknowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). if the np bit is cleared (0) while the nmi is being serviced, the newly generated intwdt2 request signal is executed (the nmi servicing is stopped). caution for the non-maskable in terrupt servicing executed by th e non-maskable interrupt request signal (intwdt2), see 16.2.2 (2 ) from intwdt2 signal. figure 16-1. non-maskable interrupt requ est signal acknowledgment operation (1/2) (a) nmi and intwdt2 request signa ls generated at the same time main routine system reset nmi and intwd t2 requests (generated simultaneously) intwd t2 servicing chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 582 figure 16-1. non-maskable interrupt requ est signal acknowledgment operation (2/2) (b) non-maskable interrupt request signal ge nerated during non-maskab le interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request signal generated during non-maskable interrupt servicing nmi intwdt2 nmi ? nmi request generated during nmi servicing ? intwdt2 request generated during nmi servicing (np bit = 1 retained before intwdt2 request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset nmi request nmi servicing (held pending) intwdt2 servicing intwdt2 request ? intwdt2 request generated during nmi servicing (np bit = 0 set before intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing intwdt2 request np = 0 ? intwdt2 request generated during nmi servicing (np = 0 set after intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing np = 0 ? intwdt2 request generated during intwdt2 servicing main routine system reset intwdt2 request intwdt2 servicing (invalid) ? nmi request generated during intwdt2 servicing intwdt2 main routine system reset intwdt2 request intwdt2 servicing (invalid) nmi request (held pending) intwdt2 request intwdt2 request chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 583 16.2.1 operation if a non-maskable interrupt request signal is generated, the cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> sets the handler address (00000010h, 00000020h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-maska ble interrupt is shown in figure 16-2. figure 16-2. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h, 0020h 1 0 1 00000010h, 00000020h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 584 16.2.2 restore (1) from nmi pin input execution is restored from the nmi se rvicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from fepc and f epsw, respectively, because the psw.ep bit is 0 and the psw.np bit is 1. <2> transfers control back to the address of the restored pc and psw. figure 16-3 illustrates how the reti instruction is processed. figure 16-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the ep and np bits are changed by the ldsr instruction during non-maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 1 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 585 (2) from intwdt2 signal restoring from non-maskable interrupt servicing exec uted by the non-maskable interrupt request (intwdt2) by using the reti instruction is disabled. execute the following software reset processing. figure 16-4. software reset processing intwdt2 occurs. fepc software reset processing address fepsw value that sets np bit = 1, ep bit = 0 reti reti 10 times (fepc and fepsw note must be set.) psw psw default value setting initialization processing intwdt2 servicing routine software reset processing routine note fepsw value that sets np bit = 1, ep bit = 0 16.2.3 np flag the np flag is a status flag that indicates that non -maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt currently being serviced np 0 1 non-maskable interrupt servicing status after reset: 00000020h chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 586 16.3 maskable interrupts maskable interrupt request signals can be masked by inte rrupt control registers. the v850es/hj2 has 64/66 maskable interrupt sources. if two or more maskable interrupt request signals ar e generated at the same ti me, they are acknowledged according to the default pr iority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (p rogrammable priority control). when an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt service routine, the interr upt enabled (ei) status is set, which enables servicing of interrupts having a higher priority t han the interrupt request signal in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to enable multiple interrupts, however, save eipc and eipsw to memory or general-purpose registers before executing the ei instruction, and execute the di instruction bef ore the reti instruction to re store the original values of eipc and eipsw. 16.3.1 operation if a maskable interrupt occurs, the cpu performs the fo llowing processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the psw. id bit to 1 and clears the psw. ep bit to 0. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal generated while another interrupt is being serviced (while the psw.np bit = 1 or the psw.id bit = 1) are held pending inside intc. in this case, servicing a new maskable interrupt is start ed in accordance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or the np and id bits are cleared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 587 figure 16-5. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address interrupt requested? note for the ispr register, see 16.3.6 in-service priority register (ispr) . chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 588 16.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is executed , the cpu performs the following steps, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and ei psw because the psw.ep bit is 0 and the psw.np bit is 0. <2> transfers control to the address of the restored pc and psw. figure 16-6 illustrates the proce ssing of the reti instruction. figure 16-6. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 16.3.6 in-service priority register (ispr) . caution when the ep and np bits are changed by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 0 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 589 16.3.3 priorities of maskable interrupts the intc performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level c ontrol: control based on the default pr iority levels, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn) of the interrupt control register (xxicn). when two or more interrupts hav ing the same priority level specified by the xxprn bit are generated at the same time, interrupt request signals are se rviced in order depending on the priority level allocated to each interrupt request type (default priority leve l) beforehand. for more information, see table 16-1 interrupt/exception source list . the programmable priority control custom izes interrupt request signals into eight levels by setting the priority level specification flag. note that when an interrupt request signal is acknowled ged, the psw.id flag is automatica lly set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 16-2 interrupt control register (xxicn) ) n: peripheral unit number (see table 16-2 interrupt control register (xxicn) ). chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 590 figure 16-7. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt request signals. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 591 figure 16-7. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 592 figure 16-8. example of servicing interrupt request signals simu ltaneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt request signals. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 593 16.3.4 interrupt control register (xxicn) the xxicn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 47h. caution disable interrupts (di) or mask the interrupt to read the xxicn.xxifn bit. if the xxifn bit is read while interrupts are enabled (ei) or while the in terrupt is unmasked, the correct value may not be read when acknowledging an interr upt and reading the bit conflict. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff1a2h 6 7 note the flag xxlfn is reset automatically by the hardwa re if an interrupt request signal is acknowledged. remark xx: identification name of each peripheral unit (see table 16-2 interrupt control registers (xxicn) ) n: peripheral unit number (see table 16-2 interrupt control registers (xxicn) ). the addresses and bits of the interrupt control registers are as follows. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 594 table 16-2. interrupt control registers (xxicn) (1/2) bit address register 7 6 5 4 3 2 1 0 fffff110h lviic lviif lvimk 0 0 0 lvipr2 lvipr1 lvipr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff122h tq0ovic tq0ovif tq0ovmk 0 0 0 tq0ovpr2 tq0ovpr1 tq0ovpr0 fffff124h tq0ccic0 tq0ccif0 tq0ccmk0 0 0 0 tq0ccpr02 tq0ccpr01 tq0ccpr00 fffff126h tq0ccic1 tq0ccif1 tq0ccmk1 0 0 0 tq0ccpr12 tq0ccpr11 tq0ccpr10 fffff128h tq0ccic2 tq0ccif2 tq0ccmk2 0 0 0 tq0ccpr22 tq0ccpr21 tq0ccpr20 fffff12ah tq0ccic3 tq0ccif3 tq0ccmk3 0 0 0 tq0ccpr32 tq0ccpr31 tq0ccpr30 fffff12ch tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff12eh tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff130h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 fffff132h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff134h tp1ccic0 tp1ccif0 tp1ccmk0 0 0 0 tp1ccpr02 tp1ccpr01 tp1ccpr00 fffff136h tp1ccic1 tp1ccif1 tp1ccmk1 0 0 0 tp1ccpr12 tp1ccpr11 tp1ccpr10 fffff138h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff13ah tp2ccic0 tp2ccif0 tp2ccmk0 0 0 0 tp2ccpr02 tp2ccpr01 tp2ccpr00 fffff13ch tp2ccic1 tp2ccif1 tp2ccmk1 0 0 0 tp2ccpr12 tp2ccpr11 tp2ccpr10 fffff13eh tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff140h tp3ccic0 tp3ccif0 tp3ccmk0 0 0 0 tp3ccpr02 tp3ccpr01 tp3ccpr00 fffff142h tp3ccic1 tp3ccif1 tp3ccmk1 0 0 0 tp3ccpr12 tp3ccpr11 tp3ccpr10 fffff144h tm0eqic0 tm0eqif0 tm0eqmk0 0 0 0 tm0eqpr02 tm0eqpr01 tm0eqpr00 fffff146h cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 fffff148h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff14ah cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff14ch cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff14eh ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff150h ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff152h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 fffff154h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff156h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff160h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff162h wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff164h wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff166h pic8 pif8 pmk8 0 0 0 ppr82 ppr81 ppr80 fffff168h pic9 pif9 pmk9 0 0 0 ppr92 ppr91 ppr90 fffff16ah pic10 pif10 pmk10 0 0 0 ppr102 ppr101 ppr100 chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 595 table 16-2. interrupt control registers (xxicn) (2/2) bit address register 7 6 5 4 3 2 1 0 fffff16ch tq1ovic tq1ovif tq1ovmk 0 0 0 tq1ovpr2 tq1ovpr1 tq1ovpr0 fffff16eh tq1ccic0 tq1ccif0 tq1ccmk0 0 0 0 tq1ccpr02 tq1ccpr01 tq1ccpr00 fffff170h tq1ccic1 tq1ccif1 tq1ccmk1 0 0 0 tq1ccpr12 tq1ccpr11 tq1ccpr10 fffff172h tq1ccic2 tq1ccif2 tq1ccmk2 0 0 0 tq1ccpr22 tq1ccpr21 tq1ccpr20 fffff174h tq1ccic3 tq1ccif3 tq1ccmk3 0 0 0 tq1ccpr32 tq1ccpr31 tq1ccpr30 fffff176h ua2ric ua2rif ua2rmk 0 0 0 ua2rpr2 ua2rpr1 ua2rpr0 fffff178h ua2tic ua2tif ua2tmk 0 0 0 ua2tpr2 ua2tpr1 ua2tpr0 fffff182h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff184h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff186h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff188h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff18ah pic11 pif11 pmk11 0 0 0 ppr112 ppr111 ppr110 fffff18ch pic12 pif12 pmk12 0 0 0 ppr122 ppr121 ppr120 fffff18eh pic13 pif13 pmk13 0 0 0 ppr132 ppr131 ppr130 fffff190h pic14 pif14 pmk14 0 0 0 ppr142 ppr141 ppr140 fffff192h tq2ovic tq2ovif tq2ovmk 0 0 0 tq2ovpr2 tq2ovpr1 tq2ovpr0 fffff194h tq2ccic0 tq2ccif0 tq2ccmk0 0 0 0 tq2ccpr02 tq2ccpr01 tq2ccpr00 fffff196h tq2ccic1 tq2ccif1 tq2ccmk1 0 0 0 tq2ccpr12 tq2ccpr11 tq2ccpr10 fffff198h tq2ccic2 tq2ccif2 tq2ccmk2 0 0 0 tq2ccpr22 tq2ccpr21 tq2ccpr20 fffff19ah tq2ccic3 tq2ccif3 tq2ccmk3 0 0 0 tq2ccpr32 tq2ccpr31 tq2ccpr30 fffff19ch cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff19eh cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff1a0h ua3ric note ua3rif ua3rmk 0 0 0 ua 3rpr2 ua3rpr1 ua3rpr0 fffff1a2h ua3tic note ua3tif ua3tmk 0 0 0 ua 3tpr2 ua3tpr1 ua3tpr0 note pd70f3711, 70f3712 only 16.3.5 interrupt mask register s 0 to 4 (imr0 to imr4) the imr0 to imr4 registers set the interrupt mask state fo r the maskable interrupts. t he xxmkn bit of the imr0 to imr4 registers is equivalent to the xxicn.xxmkn bit. the imrm register can be read or written in 16-bit units (m = 0 to 4). if the higher 8 bits of the imrm register are used as an imrmh register and the lower 8 bits as an imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 4). reset sets these registers to ffffh. caution the device file defines the xxi cn.xxmkn bit as a reserved word. if a bit is manipulated using the name of xxmkn, the contents of th e xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 596 tp0ccmk0 pmk6 imr0 (imr0h note 1 ) imr0l tp0ovmk pmk5 tq0ccmk3 pmk4 tq0ccmk2 pmk3 tq0ccmk1 pmk2 tq0ccmk0 pmk1 tq0ovmk pmk0 pmk7 lvimk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h after reset: ffffh r/w address: imr2 fffff104h, imr2l fffff104h, imr2h fffff105h ua0rmk tp3ovmk imr1 (imr1h note 1 ) imr1l cb1tmk tp2ccmk1 cb1rmk tp2ccmk0 cb0tmk tp2ovmk cb0rmk tp1ccmk1 tm0eqmk0 tp1ccmk0 tp3ccmk1 tp1ovmk tp3ccmk0 tp0ccmk1 tq1ccmk0 1 krmk ua0tmk xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr2 (imr2h note 1 ) imr2l tq1ovmk 11 pmk9 1 admk ua1tmk 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 pmk13 imr3 (imr3h note 1 ) imr3l pmk12 1 pmk11 1 dmamk3 ua2tmk dmamk2 ua2rmk tq1ccmk3 tq1ccmk2 tq1ccmk1 after reset: ffffh r/w address: imr3 fffff106h, imr3l fffff106h, imr3h fffff107h 8 1 9 dmamk0 10 dmamk1 11 12 13 14 15 1 2 3 4 5 6 7 1 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 wtimk 10 wtmk 11 pmk8 12 13 pmk10 setting of interrupt mask flag 14 15 1 ua1rmk 2 3 4 5 6 7 0 1 imr4 (imr4h note 1 ) imr4l 1 cb2rmk 1 tq2ccmk3 1 4 tq2ccmk2 1 tq2ccmk1 tq2ccmk0 tq2ovmk pmk14 after reset: ffffh r/w address: imr4 fffff108h, imr4l fffff108h, imr4h fffff109h 8 ua3rmk note 2 9 ua3tmk note 2 10 1 11 12 13 14 15 1 2 3 4 5 6 7 cb2tmk 0 notes 1. to read bits 8 to 15 of the imr0 to imr4 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of imr0h to imr4h registers. 2. pd70f3711, 70f3712 only caution set bits 15 to 10 of the imr4 register, bits 8 to 5 of the imr3 register, and bits 7 to 4 of the imr2 register to 1. if the setting of these bits is changed, the operation is not guaranteed. remark xx: identification name of each peripheral unit (see table 16-2 interrupt control registers (xxicn) ). n: peripheral unit number (see table 16-2 interrupt control registers (xxicn) ) chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 597 16.3.6 in-service priority register (ispr) the ispr register holds the priority level of the mask able interrupt currently acknowledged. when an interrupt request signal is acknowledged, the bit of this register corresponding to the priori ty level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit correspondi ng to the interrupt request signal having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non- maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of th e register have been set by acknowledging the interrupt may be read. to accu rately read the value of the ispr register before an interrupt is acknowledged, read th e register while interrupts are disabled (di). ispr7 interrupt request signal with priority n not acknowledged interrupt request signal with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah 7654 3210 remark n = 0 to 7 (priority level) chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 598 16.3.7 id flag this flag controls the maskable interr upt?s operating state, and st ores control information regarding enabling or disabling of interrupt request signals. an inte rrupt disable flag (id) is assigned to the psw. reset sets this flag to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled (pending) id 0 1 specification of maskable interrupt servicing note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and cleared to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instru ction when referencing the psw. non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. when a maskable interrupt request signal is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request signal generated during the acknowledgment disabled period (id flag = 1) is acknowledged when the xxicn.xxifn bit is set to 1, and the id flag is cleared to 0. 16.3.8 watchdog timer mode register 2 (wdtm2) this register can be read or writt en in 8-bit units (for details, see chapter 11 functions of watchdog timer 2 ). reset sets this register to 67h. 0 wdtm2 wdm21 wdm20 0 0 0 0 0 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode reset mode (initial-value) wdm21 0 0 1 wdm20 0 1 selection of watchdog timer operation mode chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 599 16.4 software exception a software exception is generated when the cpu ex ecutes the trap instruction, and can always be acknowledged. 16.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfers control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> sets the handler address (00000040h or 00000050h ) corresponding to the software exception to the pc, and transfers control. figure 16-9 illustrates the proce ssing of a software exception. figure 16-9. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction? s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 600 16.4.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instruction, t he cpu carries out the following processi ng and shifts control to the restored pc?s address. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. figure 16-10 illustrates the proce ssing of the reti instruction. figure 16-10. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep and np bits are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 1 and the np bit back to 0 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 601 16.4.3 ep flag the ep flag is a status flag used to indica te that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress. exception processing in progress. ep 0 1 exception processing status after reset: 00000020h chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 602 16.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/hj2, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 16.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to x: arbitrary caution since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follow ing processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) correspondi ng to the exception trap to the pc, and transfers control. figure 16-11 illustrates the processing of the exception trap. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 603 figure 16-11. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the db ret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. caution dbpc and dbpsw can be accessed only duri ng the interval between the execution of the dbtrap instruction and the dbret instruction. figure 16-12 illustrates the restore processing from an exception trap. figure 16-12. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 604 16.5.2 debug trap a debug trap is an exception that is generated w hen the dbtrap instruction is executed and is always acknowledged. (1) operation upon occurrence of a debug trap, the cpu performs the following processing. <1> saves restored pc to dbpc. <2> saves current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets handler address (00000060h) for debug trap to pc and transfers control. figure 16-13 shows the debug trap processing format. figure 16-13. debug trap processing format dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 605 (2) restoration restoration from a debug trap is exec uted with the dbret instruction. with the dbret instruction, the cp u performs the following steps and tran sfers control to the address of the restored pc. <1> the restored pc and psw are read from dbpc and dbpsw. <2> control is transferred to the fetc hed address of the restored pc and psw. caution dbpc and dbpsw can be accessed only duri ng the interval between the execution of the dbtrap instruction and the dbret instruction. figure 16-14 shows the processing format for restoration from a debug trap. figure 16-14. processing format of restoration from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 606 16.6 external interrupt request input pins (nmi and intp0 to intp14) 16.6.1 noise elimination (1) eliminating noise on nmi pin the nmi pin has an internal noise elimination circuit that uses analog delay. therefor e, the input level of the nmi pin is not detected as an edge unless it is maintained for a specific time or longer. therefore, an edge is detected after specific time. the nmi pin can be used to release the stop mode. in the stop mode, noise is not eliminated by using the system clock because the internal system clock is stopped. (2) eliminating noise on intp0 to intp14 pins the intp0 to intp14 pins have an internal noise elimi nation circuit that uses analog delay. therefore, the input level of the nmi pin is not detected as an edge unless it is maintained for a specific time or longer. therefore, an edge is detected after specific time. 16.6.2 edge detection the valid edge of each of the nmi and intp0 to intp 14 pins can be selected from the following four. ? rising edge ? falling edge ? both rising and falling edges ? no edge detected the edge of the nmi pin is not detected after reset. therefore, the interrupt request signal is not acknowledged unless a valid edge is enabled by using the intf0 and intr0 register (the nmi pin functions as a normal port pin). chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 607 (1) external interrupt fallin g, rising edge specification register 0 (intf0, intr0) the intf0 and intr0 registers are 8-bit registers that specify detection of the falling and rising edges of the nmi pin via bit 2 and the external interrupt pins (intp0 to intp3) via bits 3 to 6. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear the intf0n and intr0n bits to 00, and then set the port mode. 0 intf0 intf06 intp3 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: intf0 fffffc00h, intr0 fffffc20h 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 intp2 intp1 intp0 nmi intp3 intp2 intp1 intp0 nmi remark for the valid edge specification combinations, see table 16-3 . table 16-3. valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf0 n and intr0n bits to 00 if the corresponding pin is not used as the nmi or intp0 to intp3 pins. remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 608 (2) external interrupt risi ng, falling edge specificati on register 1 (intr1, intf1) the intr1 and intf1 registers are 8-bit registers that sp ecify detection of the rising and falling edges of the intp9 and intp10 pins. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear the intf1n and intr1n bits to 00, and then set the port mode. intr1 after reset: 00h r/w address: intr1 fffffc22h, intf1 fffffc02h 0 0 0 0 0 0 intr11 intr10 intf1 0 0 0 0 0 0 intf11 intf10 intp10 intp10 intp9 intp9 remark for the valid edge specification combinations, see table 16-4 . table 16-4. valid edge specification intf1n intr1n valid edge specification (n = 0, 1) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf1 n and intr1n bits to 00 if the corresponding pin is not used as the intp9 and intp10 pins. remark n = 0: control of intp9 pin n = 1: control of intp10 pin chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 609 (3) external interrupt risi ng, falling edge specificati on register 3 (intr3, intf3) the intr3 and intf3 registers are 8-bit registers that sp ecify detection of the rising and falling edges of the intp7 and intp8 pins. these registers can be read or written in 16-bit units. however, when the higher 8 bits of intf3 register are us ed as the intf3h register and the lower 8 bits as the intf3l register, they can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear the intf3n and intr3n bits to 00, and then set the port mode. intf3 (intf3h note ) after reset: 0000h r/w address: intf3 fffffc06h, intf3l fffffc06h, intf3h fffffc07h 0 0 0 0 0 0 intf39 0 (intf3l) 0 0 0 0 0 0 intf31 0 intp8 intp7 intr3 (intr3h note ) after reset: 0000h r/w address: intr3 fffffc26h, intr3l fffffc26h, intr3h fffffc27h 0 0 0 0 0 0 intr39 0 (intr3l) 0 0 0 0 0 0 intr31 0 intp8 intp7 caution when bits 8 to 15 of the intf3 and intr3 regi sters are read or written in 8-bit or 1-bit units, specify them as bits 0 to 7 of th e intf3h and intr3h registers. remark for the valid edge specification combinations, see table 16-5 . table 16-5. valid edge specification intf3n intr3n valid edge specification (n = 1, 9) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf3 n and intr3n bits to 00 if the corresponding pin is not used as the intp7 and intp8 pins. remark n = 1: control of intp7 pin n = 9: control of intp8 pin chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 610 (4) external interrupt rising , falling edge specification re gister 6l (intr6l, intf6l) the intr6l and intf6l registers are 8-bit registers that specify detection of the rising and falling edges of the intp11 to intp13 pins. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear the intf6n and intr6n bits to 00, and then set the port mode. intr6l after reset: 00h r/w address: intr6 fffffc0ch, intf6 fffffc2ch 0 0 0 0 0 intr62 intr61 intr60 intf6l 0 0 0 0 0 intf62 intt61 intf60 intp12 intp12 intp13 intp13 intp11 intp11 remark for the valid edge specification combinations, see table 16-6 . table 16-6. valid edge specification intf6n intr6n valid edge specification (n = 0 to 2) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf6 n and intr6n bits to 00 if the corresponding pin is not used as the nmi or intp11 to intp13 pins. remark n = 0: control of intp11 pin n = 1: control of intp12 pin n = 2: control of intp13 pin chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 611 (5) external interrupt fallin g, rising edge specification register 8 (intf8, intr8) the intf8 and intr8 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (intp14). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. cautions 1. when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf80 and intr80 bits to 00, and then set the port mode. 2. the intp14 pin and rxda3 pin are alternat e-function pins. when using the pin as the rxda3 pin, disable edge detection for the intp14 alternate-function pin (clear the intf8.intf80 bit and the intr8.intr80 bit to 0) . when using the pin as the intp14 pin, stop uarta3 reception (clear the ua3ctl0.ua3rxe bit to 0). intf8 after reset: 00h r/w address: intf8 fffffc10h, intr8 fffffc30h 0 0 0 0 0 0 0 intf80 intr8 0 0 0 0 0 0 0 intr80 intp14 intp14 remark for the valid edge specification combinations, see table 16-7 . table 16-7. valid edge specification intf80 intr80 valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the in tf80 and intr80 bits to 00 if the corresponding pin is not used as intp14 pin. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 612 (6) external interrupt fallin g, rising edge specification re gister 9h (intf9h, intr9h) the intf9h and intr9h registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (intp4 to intp6). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear the intf9n and intr9n bits to 0, and then set the port mode. intf9h after reset: 00h r/w address: intf9h fffffc13h, intr9h fffffc33h intf915 intf914 intf913 0 0 0 0 0 8 9 10 11 12 13 14 15 intr9h intr915 intr914 intr913 0 0 0 0 0 8 9 10 11 12 13 14 15 intp6 intp5 intp4 intp6 intp5 intp4 remark for the valid edge specification combinations, see table 16-8 . table 16-8. valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the in tf9n and intr9n bits to 00 if th e corresponding pin is not used as intp4 to intp6 pins. remark n = 13 to 15: control of intp4 to intp6 pins chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 613 (7) noise elimination control register (nfc) digital noise elimination can be selected for the intp3 pin. the noise elimination settings are performed using the nfc register. when digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, and f xt . sampling is performed three times. when digital noise elimination is selected, if the cloc k that performs sampling in the standby mode is stopped, then the intp3 interrupt request signal cannot be used for releasing the standby mode. when f xt is used as the sampling clock, the intp3 interrupt request signal can be used for releasing either the subclock operating mode or the idle1/idle2/stop/sub-idle mode. this register can be read or written in 8-bit units. reset sets this register to 00h. caution time equal to the sampling clock the number of times set by the nfsts bit is required until the digital noise eliminator is initialized afte r the sampling clock has been changed. if the valid edge of intp3 is input after the samplin g clock has been changed and before the time of the sampling clock the number of times set by the nfsts bit passes, therefore, the interrupt request signal may be generated. therefore, note the following points when using the interrupt and dma functions. ? when using the interrupt function, after the sampling clock the number of times set by the nfsts bit have elapsed , enable interrupts after the inte rrupt request flag (pic3.pif3 bit) has been cleared. ? when using the dma function (started by intp3), enable dma after the sampling clock the number of times set by the nfsts bit have elapsed. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 614 nfen nfc nfsts 0 0 0 nfc2 nfc1 nfc0 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xt (subclock) nfc2 0 0 0 0 1 1 digital sampling clock setting prohibited nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 after reset: 00h r/w address: fffff318h analog noise elimination (60 ns (typ.)) digital noise elimination nfen 0 1 settings of intp3 pin noise elimination number of times of sampling 3 times number of times of sampling twice nfsts 0 1 setting of number of times of sampling of digital noise elimination other than above remarks 1. since sampling is performed three times, the reliably eliminated noise width is 2 sampling clocks. 2. in the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 615 16.7 interrupt acknowledge time of cpu except the following cases, the interrupt acknowledge time of the cpu is 4 clocks minimum. to input interrupt request signals successively, input the next interrupt req uest signal at least 5 clocks after the preceding interrupt. ? in idle1/idle2/stop mode ? when the external bus is accessed ? when interrupt request non-sampling instructions are successively executed (see 16.8 periods in which interrupts are not acknowledged by cpu .) ? when the interrupt control register is accessed figure 16-15. pipeline operation at interr upt request signal acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt acknowledge time (internal system clock) internal interrupt external interrupt condition minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle1/idle2/stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register chapter 16 interrupt/exception processing function preliminary user?s manual u17717ej2v0ud 616 16.8 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an instru ction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instructi on and the next instruction (int errupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the prcmd register ? the store, set1, not1, or clr1 inst ructions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), interr upt mask registers 0 to 4 (imr0 to imr4) ? in-service priority register (ispr): ? command register (prcmd): ? power save control register (psc) ? on-chip debug mode register (ocdm) ? peripheral emulation register 1 (pemu1): remark xx: identification name of each peripheral unit (see table 16-2 interrupt control registers (xxicn) ) n: peripheral unit number (see table 16-2 interrupt control registers (xxicn) ). 16.9 cautions the nmi pin alternately functions as the p02 pin. it func tions as a normal port pin after reset. to enable the nmi pin, validate the nmi pin with the pmc0 re gister. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using the intf0 and intr0 registers. preliminary user?s manual u17717ej2v0ud 617 chapter 17 key interrupt function 17.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. table 17-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 17-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 chapter 17 key interrupt function preliminary user?s manual u17717ej2v0ud 618 17.2 register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 control of key return mode krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution rewrite the krm register after once clearing the krm register to 00h. remark for the alternate-function pin settings, see table 4-25 using port pin as alternate function pin . 17.3 cautions (1) if a low level is input to any of the kr0 to kr7 pins , the intkr signal is not generated even if the falling edge of another pin is input. (2) the rxda1 and kr7 pins must not be used at the same time. to use the rxda1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). (3) if the krm register is changed, an interrupt reques t signal (intkr) may be generated. to prevent this, change the krm register after disabling interrupts (di) or masking, then clear the interrupt request flag (kric.krif bit) to 0, and enable interrupts (ei) or clear the mask. (4) to use the key interrupt function, be sure to set the po rt pin to the key return pin and then enable the operation with the krm register. to switch from the key return pin to the port pin, disable the operation with the krm register and then set the port pin. preliminary user?s manual u17717ej2v0ud 619 chapter 18 standby function 18.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 18-1. table 18-1. standby modes mode functional outline halt mode mode in which only the operating clock of the cpu is stopped idle1 mode mode in which all the operations of the internal circuits except the oscillator, pll note , and flash memory are stopped idle2 mode mode in which all the internal operations of the chip except the oscillator are stopped stop mode mode in which all the internal operations of the chip except the subclock oscillator are stopped subclock operation mode mode in which the subclock is used as the internal system clock sub-idle mode mode in which all the internal operations of the chip except the oscillator are stopped, in the subclock operation mode note the pll holds the prev ious operating status. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 620 figure 18-1. status transition reset subclock operation mode (fx operates, pll operates) subclock operation mode (fx stops, pll stops) sub-idle mode (fx operates, pll operates) sub-idle mode (fx stops, pll stops) stop mode (fx stops, pll stops) idle2 mode (fx operates, pll stops) idle1 mode (fx operates, pll operates) idle1 mode (fx operates, pll stops) halt mode (fx operates, pll stops) halt mode (fx operates, pll operates) normal operation mode oscillation stabilization wait clock through mode (pll operates) clock through mode (pll stops) pll mode (pll operates) internal oscillation clock operation wdt overflow oscillation stabilization wait note pll lockup time wait oscillation stabilization wait note oscillation stabilization wait note note if a wdt overflow occurs during an oscillation st abilization time, the cpu operates on the internal oscillation clock. remark f x : main clock oscillation frequency chapter 18 standby function preliminary user?s manual u17717ej2v0ud 621 18.2 registers (1) power save control register (psc) the psc register is an 8-bit register t hat controls the standby function. the stp bit of this register is used to specify the stop mode. this regist er is a special register that can be written only by the special sequence combinations (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 psc nmi1m nmi0m intm 0 0 stp 0 76 54 32 1 0 after reset: 00h r/w address: fffff1feh standby mode release by intwdt2 signal enabled standby mode release by intwdt2 signal disabled nmi1m 0 1 standby mode release control upon occurrence of intwdt2 signal standby mode release by nmi pin input enabled standby mode release by nmi pin input disabled nmi0m 0 1 standby mode release control by nmi pin input standby mode release by maskable interrupt request signal enabled standby mode release by maskable interrupt request signal disabled intm 0 1 standby mode release control via maskable interrupt request signal normal mode standby mode stp 0 1 standby mode note setting note standby mode set by stp bit: idle1, idle2, stop, or sub-idle mode cautions 1. before setting the idle1, idle2, stop, or sub-idle mode, set the psmr.psm1 and psmr.psm0 bits and then set the stp bit. 2. settings of the nmi1m, nmi0m, and in tm bits are invalid when halt mode is released. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 622 (2) power save mode register (psmr) the psmr register is an 8-bit register that controls the opera tion status in the power save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 idle1, sub-idle modes stop, sub-idle modes idle2, sub-idle modes stop mode psm1 0 0 1 1 specification of operation in software standby mode psmr 0 0 0 0 0 psm1 psm0 after reset: 00h r/w address: fffff820h psm0 0 1 0 1 cautions 1. be sure to cl ear bits 2 to 7 to ?0?. 2. the psm0 and psm1 bits are valid only when the psc.stp bit is 1. remark idle1: in this mode, all operations except the oscillator operation and some other circuits (flash memory and pll) are stopped. after the idle1 mode is released, the norma l operation mode is restored without needing to secure the oscillation stabilization time, like the halt mode. idle2: in this mode, all operations ex cept the oscillator operation are stopped. after the idle2 mode is released, the nor mal operation mode is restored following the lapse of the setup time specified by t he osts register (flash memory and pll). stop: in this mode, all operations except the subclock oscillator operation are stopped. after the stop mode is released, the nor mal operation mode is restored following the lapse of the oscillation stabilization time specified by the osts register. sub-idle: in this mode, all other operations are halte d except for the oscillator. after the idle mode has been released by the interrupt request signal, the subclock operation mode will be restored after 12 cycles of the subclock have been secured. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 623 (3) oscillation stabilization time select register (osts) the wait time until the oscillation st abilizes after the stop mode is releas ed or the wait time until the on-chip flash memory stabilizes after the idle2 mode is released is controlled by the osts register. the osts register can be read or written 8-bit units. reset sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 4 mhz 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms 5 mhz 0.205 ms 0.410 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.107 ms f x setting prohibited note the oscillation stabilization time and set up time are required when the stop mode and idle2 mode are released, respectively. cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether th e stop mode is released by reset or the occurrence of an in terrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to ?0?. 3. the oscillation stabilization ti me following reset release is 2 16 /f x (because the initial value of the osts register = 06h). remark f x = main clock oscillation frequency chapter 18 standby function preliminary user?s manual u17717ej2v0ud 624 18.3 halt mode 18.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock s upply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 18-3 shows the operating status in the halt mode. the average current consumpt ion of the system can be reduced by usi ng the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to halt mode, but th e halt mode is then released immediately by the pending interrupt request. 18.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 14 pin input), unmasked internal interrupt request signal from a peripheral function operable in t he halt mode, or reset signal (reset by reset pin input, wdt2res signal, power-on clear circuit (poc), low-voltage de tector (lvi), or clock monitor (clm)). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the halt mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt requ est currently being serviced is issued, the halt mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt requ est currently being serviced is issued (including a non-maskable interrupt req uest signal), the halt mode is released and that interrupt request signal is acknowledged. table 18-2. operation after releasing halt mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 625 (2) releasing halt mode by reset the same operation as the normal reset operation is performed. table 18-3. operating status in halt mode setting of halt mode operating status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll operable cpu stops operation dma operable interrupt controller operable timer p (tmp0 to tmp3) operable timer q (tmq0 to tmq2) operable timer m (tmm0) operable when a clock other than f xt is selected as the count clock operable watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable csib0 to csib2 operable serial interface uarta0 to uarta3 operable a/d converter operable key interrupt function (kr) operable external bus interface see 2.2 pin states . port function retains status before halt mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 626 18.4 idle1 mode 18.4.1 setting and operation status the idle1 mode is set by clearing the psmr.psm1 and psmr .psm0 bits to 00 and setting the psc.stp bit to 1 in the normal operation mode. in the idle1 mode, the clock oscillator, pll, and flash me mory continue operating but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle1 mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on- chip peripheral functions that can operate with the subclock or an external clock continue operating. table 18-5 shows the operating status in the idle1 mode. the idle1 mode can reduce the power consumption more than the halt mode because it stops the operation of the on-chip peripheral functions. the main clock osc illator does not stop, so t he normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle1 mode has been released, in the same manner as when the halt mode is released. cautions 1. insert five or more nop instructions after the instruction th at stores data in the psc register to set the idle1 mode. 2. if the idle1 mode is set while an unmasked interrupt request signal is being held pending, the idle1 mode is released immediat ely by the pending interrupt request. 18.4.2 releasing idle1 mode the idle1 mode is released by a non-maskable interr upt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 14 pin input), unmasked internal interrupt request signal from a peripheral function operable in the idle1 mode, or reset signal (reset by reset pin input, wdt2res signal, power-on clear circuit (poc), low-voltage de tector (lvi), or clock monitor (clm)). after the idle1 mode has been released, the normal operation mode is restored. (1) releasing idle1 mode by non-maskable interr upt request signal or unmasked maskable interrupt request signal the idle1 mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle1 mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is processed as follows. cautions 1. an interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle1 mode is not released. 2. if eliminating digital noi se is selected by using the nfc re gister and if the sampling clock is selected from f xx /64, f xx /128, f xx /256, f xx /512, and f xx /1024, the idle1 mode cannot be released by the interrupt request signal of the intp3 pin. for details , see 16.6.2 (7) noise elimination control register (nfc). (a) if an interrupt request signal with a priority lower than that of the interrupt requ est currently being serviced is issued, the idle1 mode is rel eased, but that interrupt request si gnal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle1 mode is released and that interrupt request signal is acknowledged. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 627 table 18-4. operation after releasing idle1 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. (2) releasing idle1 mode by reset the same operation as the normal reset operation is performed. table 18-5. operating status in idle1 mode setting of idle1 mode operating status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll operable cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq2) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable csib0 to csib2 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 2) serial interface uarta0 to uarta3 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter holds operation (conversion result held) note key interrupt function (kr) operable external bus interface see 2.2 pin states . port function retains status before idle1 mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle1 mode was set. note to realize low power consumption, stop the a/ d converter before shifting to the idle1 mode. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 628 18.5 idle2 mode 18.5.1 setting and operation status the idle2 mode is set by setting the psmr.psm1 and psmr. psm0 bits to 10 and setting the psc.stp bit to 1 in the normal operation mode. in the idle2 mode, the clock oscillator continues operatio n but clock supply to the cpu, pll, flash memory, and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle2 mode was set are retained. the cpu, pll, and other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. table 18-7 shows the operating status in the idle2 mode. the idle2 mode can reduce the power consumption more t han the idle1 mode because it stops the operations of the on-chip peripheral functions, pll, and flash memory. however, because the pll and flash memory are stopped, a setup time for the pll and flash memory is required when idle2 mode is released. cautions 1. insert five or more nop instructions after the instruction th at stores data in the psc register to set the idle2 mode. 2. if the idle2 mode is set while an unmasked interrupt request signal is being held pending, the idle2 mode is released immediat ely by the pending interrupt request. 18.5.2 releasing idle2 mode the idle2 mode is released by a non-maskable interr upt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 14 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the idle2 mode, or reset signal (reset by reset pin input, wdt2res signal, power-on clear circuit (poc), lo w-voltage detector (lvi), or clock monitor (clm)). the pll returns to the operating status it was in before the idle2 mode was set. after the idle2 mode has been released, the normal operation mode is restored. (1) releasing idle2 mode by non-maskable interr upt request signal or unmasked maskable interrupt request signal the idle2 mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle2 mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is processed as follows. cautions 1. the interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle2 mode is not released. 2. if eliminating digital noi se is selected by using the nfc re gister and if the sampling clock is selected from f xx /64, f xx /128, f xx /256, f xx /512, and f xx /1024, the idle2 mode cannot be released by the interrupt request signal of the intp3 pin. for details , see 16.6.2 (7) noise elimination control register (nfc). (a) if an interrupt request signal with a priority lower than that of the interrupt requ est currently being serviced is issued, the idle2 mode is rel eased, but that interrupt request si gnal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle2 mode is released and that interrupt request signal is acknowledged. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 629 table 18-6. operation after releasing idle2 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the prescribed setup time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. the next instruction is executed after securing the prescribed setup time. (2) releasing idle2 mode by reset the same operation as the normal reset operation is performed. table 18-7. operating status in idle2 mode setting of idle2 mode operating status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq2) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable csib0 to csib2 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 2) serial interface uarta0 to uarta3 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter holds operation (conversion result held) note key interrupt function (kr) operable external bus interface see 2.2 pin states . port function retains status before idle2 mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle2 mode was set. note to realize low power consumption, stop the a/ d converter before shifting to the idle2 mode. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 630 18.5.3 securing setup time when releasing idle2 mode secure the setup time for the rom (f lash memory) after releasing the idle2 mode because the operation of the blocks other than the main clock oscillator stops after the idle2 mode is set. (1) releasing idle2 mode by non-maskable interr upt request signal or unmasked maskable interrupt request signal secure the specified setup time by setting the osts register. when the releasing source is generated, the dedicated in ternal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock idle mode status interrupt request (2) release by reset (reset pin input, wdt2r es generation) this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x . chapter 18 standby function preliminary user?s manual u17717ej2v0ud 631 18.6 stop mode 18.6.1 setting and operation status the stop mode is set by setting the psmr.psm1 and psmr .psm0 bits to 01 or 11 and setting the psc.stp bit to 1 in the normal operation mode. in the stop mode, the subclock oscillat or continues operating but the main cl ock oscillator stops. clock supply to the cpu and the on-chip peri pheral functions is stopped. as a result, program execution stops , and the contents of the internal ram before the stop mode was set are retained. the on-chip peripheral functi ons that operate with the clock oscillat ed by the subclock oscillator or an external clock continue operating. table 18-9 shows the operating status in the stop mode. because the stop mode stops operation of the main clock oscillator, it reduc es the power consumption to a level lower than the idle2 mode. if the subclock oscillator, inte rnal oscillator, and external clock are not used, the power consumption can be minimized with only leakage current flowing. cautions 1. insert five or more nop instructions after the instruction th at stores data in the psc register to set the stop mode. 2. if the stop mode is set while an unmasked interrupt request signal is being held pending, the stop mode is released immediatel y by the pending interrupt request. 18.6.2 releasing stop mode the stop mode is released by a non-maskable interr upt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 14 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the stop mode, or reset signal (reset by reset pin input, wdt2res signal, power-on clear circuit (poc), or low-voltage detector (lvi)). after the stop mode has been released, the normal operation mode is restor ed after the oscillation stabilization time has been secured. cautions 1. the interrupt request that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and stop mode is not released. 2. if eliminating digital noise is selected by using the nfc regist er and if the sampling clock is selected from f xx /64, f xx /128, f xx /256, f xx /512, and f xx /1024, the stop mode cannot be released by the interrupt request signal of the intp3 pin. for details, see 16.6.2 (7) noise elimination control register (nfc). (1) releasing stop mode by non-maskable interr upt request signal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the stop mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt requ est currently being serviced is issued, the stop mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than t hat of the interrupt reques t currently being serviced is issued (including a non-maskable interrupt reques t signal), the stop mode is released and that interrupt request signal is acknowledged. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 632 table 18-8. operation after releasing stop mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the oscillation stabilization time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time. the next instruction is executed after securing the oscillation stabilization time. (2) releasing stop mode by reset the same operation as the normal reset operation is performed. table 18-9. operating status in stop mode setting of stop mode operating status item when subclock is not used when subclock is used main clock oscillator stops oscillation subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq2) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r is selected as the count clock csib0 to csib2 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 2) serial interface uarta0 to uarta3 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter stops operation (conversion result undefined) notes 1, 2 key interrupt function (kr) operable external bus interface see 2.2 pin states . port function retains status before stop mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the stop mode was set. notes 1. if the stop mode is set while the a/d converter is operating, the a/d converte r is automatically stopped and starts operating again after the stop mode is releas ed. however, in that case, the a/d conversion results after the stop mode is released are invalid. all the a/d conversion results before the stop mode is set are invalid. 2. even if the stop mode is set while the a/d converte r is operating, the power consumption is reduced equivalently to when the a/d converter is stopped before the stop mode is set. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 633 18.6.3 securing oscillation stabilizati on time when releasing stop mode secure the oscillation stabilization time for the main clo ck oscillator after releasing the stop mode because the operation of the main clock oscillator stops after stop mode is set. (1) releasing stop mode by non-maskab le interrupt request signal or unmasked maskable interrupt request signal secure the oscillation stabilization time by setting the osts register. when the releasing source is generated, the dedicated in ternal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock stop status interrupt request (2) release by reset this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x . chapter 18 standby function preliminary user?s manual u17717ej2v0ud 634 18.7 subclock operation mode 18.7.1 setting and operation status the subclock operation mode is set by setting the pcc.ck3 bit to 1 in the normal operation mode. when the subclock operation mode is set, t he internal system clock is changed from the main clock to the subclock. check whether the clock has been s witched by using the pcc.cls bit. when the pcc.mck bit is set to 1, the operation of the main clock oscillator is stopped. as a result, the system operates only on the subclock. in the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is us ed as the internal system clock. in addition, the power consumption can be further reduced to the level of the stop mode by st opping the operation of t he main clock oscillator. table 18-10 shows the operating st atus in subclock operation mode. cautions 1. when manipulating the ck3 bit, do not ch ange the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to manipul ate the bit is recommended). for details of the pcc register, see 6.3 (1) pro cessor clock control register (pcc). 2. if the following conditions are not satisfied, ch ange the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt = 32.768 khz) 4 remark internal system clock (f clk ): clock generated from main clock (f xx ) in accordance with the settings of the ck2 to ck0 bits 18.7.2 releasing subclock operation mode the subclock operation mode is released by a reset sign al (reset by reset pin input, wdt2res signal, power-on clear circuit (poc), low-voltage detector (lvi), or cl ock monitor (clm)) when the ck3 bit is cleared to 0. if the main clock is stopped (mck bit = 1), set the mck bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1 ) processor clock control register (pcc). chapter 18 standby function preliminary user?s manual u17717ej2v0ud 635 table 18-10. operating status in subclock operation mode operating status setting of subclock operation mode item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled internal oscillator oscillation enabled pll operable stops operation note cpu operable dma operable interrupt controller operable timer p (tmp0 to tmp3) operable stops operation timer q (tmq0 to tmq2) operable stops operation timer m (tmm0) operable operable when f r /8 or f xt is selected as the count clock watch timer operable operable when f xt is selected as the count clock watchdog timer 2 operable operable when f r is selected as the count clock csib0 to csib2 operable operable when the sckbn input clock is selected as the count clock (n = 0 to 2) serial interface uarta0 to uarta3 operable stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter operable stops operation key interrupt function (kr) operable external bus interface see 2.2 pin states . port function settable internal data settable note be sure to stop the pll (pllctl.pllon = 0) before stopping the main clock. caution when the cpu is operati ng on the subclock and main cloc k oscillation is stopped, accessing a register in which a wait occurs is disabled. if a wait is generated, it can be released only by reset (see 3.4.8 (2)). chapter 18 standby function preliminary user?s manual u17717ej2v0ud 636 18.8 sub-idle mode 18.8.1 setting and operation status the sub-idle mode is set by setting the psmr.psm1 a nd psmr.psm0 bits to 00 or 10 and setting the psc.stp bit to 1 in the subclock operation mode. in this mode, the clock oscillator c ontinues operating but clock supply to the cpu, flash memory, and the other on- chip peripheral functions is stopped. as a result, program execution stops and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip peripheral functions are stopped. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. because the sub-idle mode stops oper ation of the cpu, flash memory, and ot her on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. if the sub-idle mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the stop mode. table 18-12 shows the operating status in the sub-idle mode. cautions 1. following the store inst ruction to set the psc register to the sub-idle mode, insert five or more nop instructions. 2. if the sub-idle mode is set while an unmasked interrupt request signal is being held pending, the sub-idle mode is then released immediately by the pending interrupt request. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 637 18.8.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable inte rrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 14 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-idle mode, or reset signal (reset by reset pin input, wdt2res signal, power-on clear circuit (poc), lo w-voltage detector (lvi), or clock monitor (clm)). the pll returns to the operating status it was in bef ore the sub-idle mode was set. when the sub-idle mode is released by an interrupt request signal, the subclock operation mode is set. (1) releasing sub-idle m ode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the pr iority of the interrupt request signal. if the sub-idle mode is set in an inte rrupt servicing routine, however, an in terrupt request signal that is issued later is serviced as follows. cautions 1. the interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and sub-idle mode is not released. 2. when the sub-idle mode is relea sed, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signal that releases the sub-idle mode is generated to when the mode is released. 3. if eliminating digital noi se is selected by using the nfc re gister and if the sampling clock is selected from f xx /64, f xx /128, f xx /256, f xx /512, and f xx /1024, the sub-idle mode cannot be released by the interrupt request signal of the intp3 pin. for details , see 16.6.2 (7) noise elimination control register (nfc). (a) if an interrupt request signal with a priority lower than that of the interrupt requ est currently being serviced is issued, the sub-idle mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt requ est currently being serviced is issued (including a non-maskable interrupt reques t signal), the sub-idle mode is released and that interrupt request signal is acknowledged. table 18-11. operation after releasing sub- idle mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. chapter 18 standby function preliminary user?s manual u17717ej2v0ud 638 (2) releasing sub-idle mode by reset the same operation as the normal reset operation is performed. table 18-12. operating status in sub-idle mode setting of sub-idle mode operating status item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled internal oscillator oscillation enabled pll operable stops operation note 1 cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq2) stops operation timer m (tmm0) operable when f r /8 or f xt is selected as the count clock watch timer stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r is selected as the count clock csib0 to csib2 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 2) serial interface uarta0 to uarta3 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter holds operation (conversion result held) note 2 key interrupt function (kr) operable external bus interface see 2.2 pin states (same operation status as idle1, idle2 mode). port function retains status before sub-idle mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. notes 1. be sure to stop the pll (pllctl.pllon bi t = 0) before stopping the main clock. 2. to realize low power consumpti on, stop the a/d converter before shifting to the sub-idle mode. preliminary user?s manual u17717ej2v0ud 639 chapter 19 reset functions 19.1 overview the following reset functions are available. (1) four kinds of reset sources ? external reset input via the reset pin ? reset via the watchdog timer 2 (wdt2) overflow (wdt2res) ? system reset via the comparison of the low-volt age detector (lvi) supply voltage and detected voltage ? system reset via the detecting clock monitor (clm) oscillation stop ? system reset via the power-on clear circuit after a reset is released, the source of the reset can be confirmed with the reset source flag register (resf). (2) emergency operation mode if the wdt2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock oscillation anomaly is judged and the cpu starts operating on the internal oscillation clock. caution when the cpu is being operated with the inte rnal oscillation clock, access to the register in which a wait state is generated is prohibited. for the register in which a wait state is generated, see 3.4.8 (2) accessing speci fic on-chip peripheral i/o registers. chapter 19 reset functions preliminary user?s manual u17717ej2v0ud 640 19.2 registers to check reset source the v850es/hj2 has four kinds of reset sources. after a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (resf). (1) reset source flag register (resf) the resf register is a special regist er that can be written only by a comb ination of specific sequences (see 3.4.7 special registers ). the resf register indicates the source from which a reset signal is generated. this register is read or written in 8-bit or 1-bit units. reset pin input or poc reset sets this register to 00h. the default value differs if t he source of reset is other than the reset pin signal. 0 wdt2rf 0 1 not generated generated resf 0 0 wdt2rf 0 0 clmrf lvirf after reset: 00h note r/w address: fffff888h reset signal from wdt2 lvirf 0 1 not generated generated reset signal from lvi clmrf 0 1 not generated generated reset signal from clm note the value of the resf register is cleared to 00h when a reset is executed via the reset pin. when a reset is executed by watchdog timer 2 (wdt2), low-vo ltage detector (lvi), or clock monitor (clm), the reset flags of this register (wdt2rf bit, clmrf bit, and lvirf bit) are set. however, other sources are retained. caution only ?0? can be written to each bit of this register. if writing ?0? conflicts with setting the flag (occurrence of reset), setting the flag takes precedence. chapter 19 reset functions preliminary user?s manual u17717ej2v0ud 641 19.3 operation 19.3.1 reset operation via reset pin when a low level is input to the reset pin, the syst em is reset, and each hardware unit is initialized. when the level of the reset pin is changed from low to high, the reset status is released. table 19-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts crystal oscillation oscillation continues subclock oscillator (f xt ) rc oscillation oscillation stops oscillation starts internal oscillator oscillation stops oscillation starts peripheral clock (f x to f x /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts after securing oscillation stabilization time watchdog timer 2 operation stops (ini tialized to 0) operation starts internal ram undefined if power-on reset or cpu access and reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained note 1 . i/o lines (ports/alternate- function pins) high impedance note 2 on-chip peripheral i/o registers initialized to sp ecified status, ocdm register is set (01h). other on-chip peripheral functions operation st ops operation can be started after securing oscillation stabilization time notes 1. the firmware of the v850es/hj2 uses a part of the internal ram after the internal system reset status has been released because it supports a boot swap function. therefore, the contents of some ram areas (ram size: 20 kb (3ffa000h to 3ffa095h), ram size: 12 kb (3ffc000h to 3ffc095h)) are not retained after power-on reset. 2. when the power is turned on, the following pin may output an undefined level temporarily even during reset. ? p53/kr3/tiq00/toq00/ddo pin caution the ocdm register is initialized by the reset pin input. therefore, note with caution that, if a high level is input to the p05/drst pin after a reset release before the ocdm.ocdm0 bit is cleared, the on-chip debug mode is entered. for details, see chapter 4 port functions. chapter 19 reset functions preliminary user?s manual u17717ej2v0ud 642 figure 19-1. timing of reset operation by reset pin input counting of oscillation stabilization time initialized to f xx /8 operation oscillation stabilization timer overflows internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay figure 19-2. timing of power-on reset operation oscillation stabilization time count must be on-chip regulator stabilization time (1 ms (max.)) or longer. initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal reset f x v dd f clk analog delay chapter 19 reset functions preliminary user?s manual u17717ej2v0ud 643 19.3.2 reset operation by watchdog timer 2 when watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (wdt2res signal generati on), a system reset is executed and the hardware is initialized to the initial status. following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released. the main clock oscillator is stopped during the reset period. table 19-2. hardware status during watchdog timer 2 reset operation item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts crystal oscillation oscillation continues subclock oscillator (f xt ) rc oscillation oscillation stops oscillation starts internal oscillator oscillation stops oscillation starts peripheral clock (f xx to f xx /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution after securing oscillation stabilization time watchdog timer 2 operation stops (ini tialized to 0) operation starts internal ram undefined if power-on reset or cpu access and reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained note . i/o lines (ports/alternate- function pins) high impedance on-chip peripheral i/o register initialized to spec ified status, ocdm register retains its value. on-chip peripheral functions other than above operation stops operation can be started after securing oscillation stabilization time. note the firmware of the v850es/hj2 uses a part of the in ternal ram after the internal system reset status has been released because it supports a boot swap function. therefore, the contents of some ram areas (ram size: 20 kb (3ffa000h to 3ffa095h), ram size: 12 kb (3ffc000h to 3ffc095h)) are not retained after power-on reset. chapter 19 reset functions preliminary user?s manual u17717ej2v0ud 644 19.3.3 reset operation by power-on clear circuit the supply voltage and detection voltage are compared w hen the power-on clear operation is enabled. if the supply voltage drops below the detection voltage (inclu ding when power is applied), the system is reset and each hardware unit is initializ ed to the default status. the reset status lasts since the voltage drop has been det ected until the supply volta ge rises above the detection voltage, and then is automatica lly cleared. after the reset status is clear ed, time to stabilize oscillation of the main clock oscillator (default value of osts register: 2 16 /f x ) elapses, and then the cpu star ts program execution. for details, see chapter 21 power-on clear circuit . 19.3.4 reset operation by low-voltage detector when lvi operation is enabled and when the lvim.lvimd bi t is set to ?1?, the supply voltage and detection voltage are compared. if the supply voltage drops below the detecti on voltage, the system is reset and each hardware unit is initialized to the default status. the reset status lasts from detection of the voltage drop until the supply vo ltage rises above the detection voltage, and then is automatically cleared. after the reset status is cleared, time to stabilize oscillation of the main clock oscillator (default value of osts register: 2 16 /f x ) elapses, and then the cpu st arts program execution. for details, see chapter 22 low-voltage detector . 19.3.5 reset operation by clock monitor when the clock monitor operation is enabled, the main clo ck is monitored by using the sampling clock (internal oscillator). if stoppage of the main cl ock is detected, the system is reset and eac h hardware unit is initialized to the default status. for details, see chapter 20 clock monitor . preliminary user?s manual u17717ej2v0ud 645 chapter 20 clock monitor 20.1 functions the clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. when a reset by the clock monitor occurs, the resf.clmrf bit is set. for details on the resf register, see 19.2 registers to check reset source . the clock monitor automatically stops under the following conditions. ? during oscillation stabilization time after stop mode is released ? when the main clock is stopped (from when the pcc.mck bit = 1 during subclock operation, until the pcc.cls bit = 0 during main clock operation) ? when the sampling clock (internal oscillation clock) is stopped ? when the cpu operates with the internal oscillation clock 20.2 configuration the clock monitor includes the following hardware. table 20-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 20-1. block diagram of clock monitor main clock internal oscillation clock internal reset signal enable/disable clme clock monitor mode register (clm) chapter 20 clock monitor preliminary user?s manual u17717ej2v0ud 646 20.3 register the clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) the clm register is a special regist er. this can be written only in a s pecial combination of sequences (see 3.4.7 special register ). this register is used to set the operation mode of the clock monitor. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: fffff870h 7 6 5 4 3 2 1 0 clm 0 0 0 0 0 0 0 clme clme clock monitor operation enable or disable 0 disable clock monitor operation. 1 enable clock monitor operation. cautions 1. once the clme bit h as been set to 1, it cannot be cleared to 0 by any means other than reset. 2. when a reset by the clock monitor occu rs, the clme bit is cleared to 0 and the resf.clmrf bit is set to 1. chapter 20 clock monitor preliminary user?s manual u17717ej2v0ud 647 20.4 operation this section explains the functions of the clock m onitor. the start and stop conditions are as follows. chapter 20 clock monitor preliminary user?s manual u17717ej2v0ud 648 (1) operation when main clock osc illation is stopped (clme bit = 1) if oscillation of the main clock is stopped when the clme bit = 1, an internal reset signal is generated as shown in figure 20-2. figure 20-2. reset period due to that oscillation of main clock is stopped four internal oscillation clocks main clock internal oscillation clock internal reset signal clm.clme bit resf.clmrf bit (2) clock monitor status after reset input reset input clears the clm.clme bit to 0 and stops the cl ock monitor operation. when clme bit is set to 1 by software at the end of the oscillation stabilization time of the main clock, monitoring is started. figure 20-3. clock monitor status after reset input (clm.clme bit = 1 is set after reset input and at the end of main clock oscillation stabilization time) cpu operation clock monitor status clme reset internal oscillation clock main clock reset oscillation stabilization time normal operation clock supply stopped normal operation monitoring monitoring stopped monitoring set to 1 by software chapter 20 clock monitor preliminary user?s manual u17717ej2v0ud 649 (3) operation in stop mode or after stop mode is released if the stop mode is set with the clm.clme bit = 1, the monitor operation is stopped in the stop mode and while the oscillation stabilization ti me is being counted. after the osc illation stabilization time, the monitor operation is automatically started. figure 20-4. operation in stop mode or after stop mode is released clock monitor status during monitor monitor stops during monitor clme internal oscillation clock main clock cpu operation normal operation stop oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) (4) operation when main clock is stopped (arbitrary) during subclock operation (pcc.cls bit = 1) or when the main clock is stopped by setting the pcc.mck bit to 1, the monitor operation is stopped until the main cloc k operation is started (pcc.cls bit = 0). the monitor operation is automatically started when the main clock operation is started. figure 20-5. operation when main clock is stopped (arbitrary) clock monitor status during monitor monitor stops monitor stops during monitor clme internal oscillation clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time (set by osts register) oscillation stabilization time count by software pcc.mck bit = 1 (5) operation while cpu is operating on inte rnal oscillation clock (ccls.cclsf bit = 1) the monitor operation is not stopped when the cclsf bi t is 1, even if the clme bit is set to 1. preliminary user?s manual u17717ej2v0ud 650 chapter 21 power-on clear circuit 21.1 function functions of the power-on-clear (poc) circuit are shown below. ? generates a reset signal upon power application. ? compares the supply voltage (v dd ) and detection voltage (v poc0 ), and generates a reset signal when v dd < v poc0 (detection voltage (v poc0 ): 3.7 v 0.2 v). remarks 1. the v850es/hj2 has plural internal hardware units that generate an internal reset signal. when the system is reset by watchdog timer 2 (wdt2res), low-voltage detector (lvi), or clock monitor (clm), a flag corresponding to the reset source is alloca ted to the reset source flag register (resf). the resf register is not cleared when an inter nal reset signal is generated by wdt2res, lvi, or clock monitor, and its flag corresponding to the reset source is set to 1. for details of the resf register, see chapter 19 reset functions . 2. the time from power application to starting prog ram execution is ?time from power application to releasing reset + 16 ms? if the operating frequency of a resonator externally connected is 5 mhz. however, it varies depending on the external ca use (such as a status of supply voltage to the microcontroller and the stabilizati on time of the resonator). 21.2 configuration the block diagram is shown below. figure 21-1. block diagram of power-on-clear circuit ? + detection voltage source (v poc0 ) internal reset signal v dd chapter 21 power-on clear circuit preliminary user?s manual u17717ej2v0ud 651 21.3 operation when the supply voltage and detection voltage are compared and if the supply voltage is lower than the detection voltage (including at power application), the system is reset and each hardware is returned to the specific status. figure 21-2. timing of reset signal generation by power-on-clear circuit delay time reset period (excluding oscillation stabilization time) reset period (excluding oscillation stabilization time) reset period (excluding oscillation stabilization time) internal reset signal poc detection signal supply voltage (v dd ) poc detection voltage (v poc0 ) preliminary user?s manual u17717ej2v0ud 652 chapter 22 low-voltage detector 22.1 functions the low-voltage detector (lvi) has the following functions. ? compares the supply voltage (v dd ) and detection voltage (v lv i ) and generates an interrupt request signal or internal reset signal when v dd < v lv i . ? the level of the supply voltage to be detec ted can be changed by software (in two steps). ? an interrupt request signal or internal reset signal can be selected. ? can operate in stop mode. ? operation can be stopped by software. if the low-voltage detector is used to generate a reset signal, the resf.lvirf bit is set to 1 when the reset signal is generated. for details of resf register, see chapter 19 reset functions . 22.2 configuration the block diagram is shown below. figure 22-1. block diagram of low-voltage detector lvis0 lvion detection voltage source (v lvi ) v dd v dd intlvi internal bus n-ch low-voltage detection level select register (lvis) low-voltage detection register (lvim) lvimd lvif internal reset signal selector low- voltage detection level selector ? + chapter 22 low-voltage detector preliminary user?s manual u17717ej2v0ud 653 22.3 registers (1) low-voltage detection register (lvim) the lvim register is used to enable or disable low voltag e detection, and to set the operation mode of the low- voltage detector. the lvim register is a special register. it can be written only by a combination of specific sequences (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. however, bit 0 is read-only. after reset: 00h r/w address: fffff890h 7 6 5 4 3 2 1 0 lvim lvion 0 0 0 0 0 lvimd lvif lvion low voltage detection operation enable or disable 0 disable operation. 1 enable operation. lvimd selection of operation mode of low voltage detection 0 generate interrupt request signal intlvi when supply voltage < detection voltage. 1 generate internal reset signal lvires when supply voltage < detection voltage. lvif low voltage detection flag 0 when supply voltage > detection voltage, or when operation is disabled 1 supply voltage < detection voltage cautions 1. after setting the lvion bit to 1, wait for 0.2 ms (typ.) (target value) before checking the voltage using the lvif bit. 2. the value of the lvif flag is output as the output signal intlvi when the lvion bit = 1 and lvimd bit = 0. 3. be sure to clear bits 2 to 6 to ?0?. chapter 22 low-voltage detector preliminary user?s manual u17717ej2v0ud 654 (2) low-voltage detection level select register (lvis) the lvis register is used to select t he level of low voltage to be detected. this register can be read or written in 8-bit units. after reset: 00h r/w address: fffff891h 7 6 5 4 3 2 1 0 lvis 0 0 0 0 0 0 0 lvis0 lvis0 detection level 0 4.4 v 0.2 v 1 4.2 v 0.2 v cautions 1. this register cannot be written until a reset request due to something other than low-voltage detection is generated after the lvim.lvion and lvim.lvimd bits are set to 1. 2. be sure to clear bits 1 to 7 to ?0?. (3) internal ram data status register (rams) the rams register is a flag regist er that indicates whether the internal ram is valid or not. the rams register is a special register. it can be written only by a combination of specific sequences (see 3.4.7 special registers ). for the rams register, see 22.5 ram retention voltage detection operation . this register can be read or written in 8-bit or 1-bit units. caution the following shows the specific sequence after reset. ? setting conditions: detection of voltage lower than detection level set by instruction generation of reset signa l by watchdog timer overflow generation of reset signa l while ram is being accessed generation of reset signal by clock monitor ? clearing condition: writing of 0 in specific sequence after reset: 01h r/w address: fffff892h 7 6 5 4 3 2 1 0 rams 0 0 0 0 0 0 0 ramf ramf internal ram data valid/invalid 0 valid 1 invalid chapter 22 low-voltage detector preliminary user?s manual u17717ej2v0ud 655 22.4 operation depending on the setting of the lvim.lvimd bit, an interrupt re quest signal (intlvi) or an internal reset signal is generated. 22.4.1 to use for inte rnal reset signal chapter 22 low-voltage detector preliminary user?s manual u17717ej2v0ud 656 figure 22-2. operation timing of low-voltage detector (lvimd bit = 1) set (by instruction, refer to <3> above) lvi reset request signal lvirf bit note 1 poc detection voltage supply voltage (v dd ) lvi detection voltage lvion bit lvi detection signal poc reset request signal internal reset signal (active low) clear (by poc reset request signal) time delay delay delay note 2 delay delay delay delay delay cleared by instruction notes 1. the lvirf bit is bit 0 of the reset source fl ag register (resf). for details of resf, see chapter 19 reset functions . 2. during the period in which the supply voltage is the set voltage or lower, the internal reset signal is retained (internal reset state). chapter 22 low-voltage detector preliminary user?s manual u17717ej2v0ud 657 22.4.2 to use for interrupt chapter 22 low-voltage detector preliminary user?s manual u17717ej2v0ud 658 22.5 ram retention voltage detection operation the supply voltage and detection voltage are compared. when the supply voltage drops below the detection voltage (including on power application), the rams.ramf bit is set (1). when the poc function is not used and when the ram ret ention voltage detection function is used, be sure to input an external reset signal if the detec ted voltage falls below the operating voltage. figure 22-4. operation timing of ram retention voltage detection function supply voltage (v dd ) poc detection voltage ram retention detection voltage poc detection voltage set condition detection signal ram retention voltage detection signal ram retention flag (ramf bit) delay delay delay time note delay set set cleared by instruction cleared by instruction note a reset signal (wdtres) is generated due to an ov erflow of the watchdog timer or reset pin input during ram access. chapter 22 low-voltage detector preliminary user?s manual u17717ej2v0ud 659 22.6 emulation function when an in-circuit emulator is used, the operation of the ram retention flag (rams.ramf bit) can be pseudo- controlled and emulated by manipulating the pemu1 register on the debugger. this register is valid only in the emulation mode. it is invalid in the normal mode. (1) peripheral emulation register 1 (pemu1) after reset: 00h r/w address: fffff9feh 7 6 5 4 3 2 1 0 pemu1 0 0 0 0 0 evaramin 0 0 evaramin pseudo specification of ram retention voltage detection signal 0 do not detect voltage lower than ram retention voltage. 1 detect voltage lower than ram retention voltage (set ramf flag). caution this bit is not automatically cleared. [usage] when an in-circuit emulator is used, pseudo emulation of ramf is realized by rewriting this register on the debugger. <1> cpu break (cpu operation stops.) <2> set the evaramin bit to 1 by using a register write command. by setting the evaramin bit to 1, the ramf bit is se t to 1 on hardware (the internal ram data is invalid). <3> clear the evaramin bit to 0 by using a register write command again. unless this operation is performed (clearing the evaram in bit to 0), the ramf bit cannot be cleared to 0 by a cpu operation instruction. <4> run the cpu and resume emulation. preliminary user?s manual u17717ej2v0ud 660 chapter 23 regulator 23.1 overview the v850es/hj2 includes a regulator to reduce power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter and output buffers). the regulator output voltage is set to 2.5 v (typ.). figure 23-1. regulator bv dd av ref0 flmd0 v dd ev dd regc ev dd i/o buffer bidirectional level shifter bv dd i/o buffer regulator a/d converter flash memory main/sub oscillator internal digital circuits 2.5 v (typ.) chapter 23 regulator preliminary user?s manual u17717ej2v0ud 661 23.2 operation the regulator of this product always operates in any mode (normal oper ation mode, halt mode, idle1 mode, idle2 mode, stop mode, or during reset). be sure to connect a capacitor (4.7 f (preliminary value)) to the regc pin to stabilize the regulator output. a diagram of the regulator pin connection method is shown below. figure 23-2. regc pin connection reg v dd v ss regc input voltage = 3.5 to 5.5 v voltage supply to main oscillator/internal logic = 2.5 v (typ.) 4.7 f (preliminary value) preliminary user?s manual u17717ej2v0ud 662 chapter 24 flash memory the following can be considered as the development en vironment and mass production applications using flash memory versions. for altering software after the v850es/ hj2 is soldered onto the target system. for data adjustment when starting mass production. for differentiating software according to the specif ication in small scale production of various models. for facilitating inventory management. for updating software after shipment. 24.1 features 4-byte/1-clock access (when instruction is fetched) capacity: 512/376/256/128 kb write voltage: erase/write with a single power supply rewriting method ? rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) flash memory write prohibit f unction supported (security function) safe rewriting of entire flash memory area by self programming using boot swap function interrupts can be acknowledged during self programming. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 663 24.1.1 erasure unit the units in which the 512, 376, 256, or 12 8 kb flash memory can be erased are as follows. (1) all-area erasure the flash memory areas can be erased at the same time. (2) block erasure the flash memory can be erased in block units note . block 0: 56 kb block 1: 8 kb block 2: 56 kb block 3: 8 kb block 4: 56 kb block 5: 56 kb block 6: 8 kb block 7: 8 kb block 8: 60 kb block 9: 60 kb block 10: 60 kb block 11: 60 kb block 12: 4 kb block 13: 4 kb block 14: 4 kb block 15: 4 kb note 4 blocks, blocks 0 to 3, for the 128 kb version ( pd70f3709). 8 blocks, blocks 0 to 7, for the 256 kb version ( pd70f3710). 10 blocks, blocks 0 to 9, for the 376 kb version ( pd70f3711). 16 blocks, blocks 0 to 15, for the 512 kb version ( pd70f3712). chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 664 24.2 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedicat ed flash programmer after the v850es/hj2 is mounted on the target system (on-board pr ogramming). the flash memory can also be re written before the device is mounted on the target system (off-board progr amming) by using a dedicated program adapter (fa series). 24.2.1 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850es/hj2. figure 24-1. environment required fo r writing programs to flash memory host machine rs-232c dedicated flash programmer v850es/hj2 flmd1 v dd v ss reset uarta0/csib0 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve flmd0 usb a host machine is required for controlling the dedicated flash programmer. uarta0 or csib0 is used for the interface between the dedicated flas h programmer and the v850es/hj2 to perform writing, erasing, etc. a dedicated program adapter (fa series ) required for off-board writing. remark the fa series is a product of naito densei machida mfg. co., ltd. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 665 24.2.2 communication mode communication between the dedicated flash programm er and the v850es/hj2 is performed by serial communication using the uarta0 or cs ib0 interfaces of the v850es/hj2. (1) uarta0 transfer rate: 9,600 to 153,600 bps figure 24-2. communication with dedicated flash programmer (uarta0) dedicated flash programmer v850es/hj2 v dd v ss reset txda0 rxda0 flmd1 flmd1 v dd gnd reset rxd txd pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve flmd0 flmd0 cautions 1. process the pins not shown in compliance with the pro cessing of unused pins (see 2.4 pin i/o circuit types and recommended connectio n of unused pins). connect a resistor of 1 k ? to 10 k ? as necessary. 2. do not input a high level to the drst pin. (2) csib0 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 24-3. communication with de dicated flash programmer (csib0) dedicated flash programmer v850es/hj2 flmd1 v dd v ss reset sob0 sib0 sckb0 flmd1 v dd gnd reset si so sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx yy y x x x x x x x x x x x x x x x xxx x y yyy statve flmd0 flmd0 cautions 1. process the pins not shown in compliance with the pro cessing of unused pins (see 2.4 pin i/o circuit types and recommended connectio n of unused pins). connect a resistor of 1 k ? to 10 k ? as necessary. 2. do not input a high level to the drst pin. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 666 (3) csib0 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 24-4. communication with dedi cated flash programmer (csib0 + hs) dedicated flash programmer v850es/hj2 v dd v ss reset sob0 sib0 sckb0 pcm0 v dd flmd1 flmd1 gnd reset si so sck hs pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve flmd0 flmd0 cautions 1. process the pins not shown in compliance with the processi ng of unused pins (see 2.4 pin i/o circuit types and recommended connection of unused pins). connect a resistor of 1 k ? to 10 k ? as necessary. 2. do not input a high level to the drst pin. the dedicated flash programmer outputs the transfer clock, and the v850es/hj2 operates as a slave. when the pg-fp4 is used as the d edicated flash programmer, it gener ates the following signals to the v850es/hj2. for details, refer to the pg-fp4 user?s manual (u15260e) . table 24-1. signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850es/hj2 processing for connection signal name i/o pin function pin name uarta0 csib0 csib0 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/hj2 x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal sob0, txda0 so/txd output transmit signal sib0, rxda0 sck output transfer clock sckb0 hs input handshake signal for csib0 + hs communication pcm0 notes 1. wire these pins as shown in figure 24-5, or connect then to gnd via pull-down resistor on board. 2. clock cannot be supplied via the clk pin of the flash programmer. create an oscillator on board and supply the clock. remark : must be connected. : does not have to be connected. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 667 table 24-2. wiring of flash writing adapter for v850es/hj2 (fa-144gj-uen) flash programmer (pg-fp4) connection pins when csib0 + hs is used when csib0 is used when uarta0 is used signal name i/o pin function pin name on fa board pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal si p41/sob0 23 p41/sob0 23 p30/txda0 25 so/txd output transmit signal so p40/sib0 22 p40/sib0 22 p31/rxda0/intp7 26 sck output transfer clock sck p42/sckb0 24 p42/sckb0 24 not necessary ? x1 not necessary ? not necessary ? not necessary ? clk output clock to v850es/hj2 x2 not necessary ? not necessary ? not necessary ? /reset output reset signal /reset reset 14 reset 14 reset 14 flmd0 input write voltage flmd0 flmd0 8 flmd0 8 flmd0 8 flmd1 input write voltage flmd1 pdl5/ad5/flmd1 110 pdl5/ad5/flmd1 110 pdl5/ad5/flmd1 110 hs input handshake signal of csi0 + hs communication reserve / hs pcm0/wait 85 not necessary ? not necessary ? v dd 9 v dd 9 v dd 9 bv dd 104 bv dd 104 bv dd 104 ev dd 5, 34 ev dd 5, 34 ev dd 5, 34 vdd ? vdd voltage generation/ voltage monitor vdd av ref0 1 av ref0 1 av ref0 1 v ss 11 v ss 11 v ss 11 av ss 2 av ss 2 av ss 2 bv ss 103 bv ss 103 bv ss 103 gnd ? ground gnd ev ss 33 ev ss 33 ev ss 33 cautions 1. be sure to conn ect the regc pin to gnd via a 4.7 f (preliminary value) capacitor. 2. a clock cannot be supplied from the clk pin of the flash programmer. create an oscillator on the board and supply the clock from that oscillator. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 668 figure 24-5. example of wi ring of v850es/hj2 flash writ ing adapter (fa-144gj-uen) (in csib0 + hs mode) (1/2) v850es/hj2 vdd gnd gnd vdd gnd vdd vdd gnd connect to vdd connect to gnd 25 30 20 15 75 80 85 90 95 100 105 35 40 45 50 55 60 65 70 110 115 120 125 130 135 140 1 5 10 rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs x1 x2 note 2 note 1 note 3 4.7 f (preliminary value) chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 669 figure 24-5. example of wi ring of v850es/hj2 flash writ ing adapter (fa-144gj-uen) (in csib0 + hs mode) (2/2) notes 1. wire the flmd1 pin as shown below, or connect it to gnd on board via a pull-down resistor. 2. pins used when uarta0 is used 3. supply a clock by creating an oscillator on the fl ash writing adapter (enclos ed by the broken lines). here is an example of the oscillator. example x1 x2 caution do not input a high level to the drst pin. remarks 1. process the pins not shown in accord ance with processing of unused pins (see 2.4 pin i/o circuit types and recommended connection of unused pins ). 2. this adapter is used for the 144-pin plastic lqfp package. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 670 24.2.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 24-6. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 671 24.2.4 selection of communication mode in the v850es/hj2, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 24-7. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxda0 (input) txda0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uarta0 communication rate: 9,600 bps (after reset), lsb first 8 csib0 v850es/hj2 performs slave operation, msb first 11 csib0 + hs v850es/hj2 performs slave operation, msb first other rfu setting prohibited caution when uarta0 is selected , the receive clock is calculate d based on the reset command sent from the dedicated flash programme r after receiving the flmd0 pulse. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 672 24.2.5 communication commands the v850es/hj2 communicates with the dedicated flash programmer by means of commands. the signals sent from the dedicated flash programmer to the v850es/hj2 are called ?commands?. the response signals sent from the v850es/hj2 to the dedicated flash programmer are called ?response commands?. figure 24-8. communication commands dedicated flash programmer v850es/hj2 command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve the following shows the commands for flash memory cont rol in the v850es/hj2. all of these commands are issued from the dedicated flash progr ammer, and the v850es/hj2 performs t he processing corresponding to the commands. table 24-3. flash memory control commands support classification command name csib0 csib0 + hs uarta0 function blank check block blank check command checks if the contents of the memory in the specified block have been correctly erased. chip erase command erases the contents of the entire memory. erase block erase command erases the contents of the memory of the specified block. write write command writes the specified address range, and executes a contents verify check. verify command compares the contents of memory in the specified address range with data transferred from the flash programmer. verify checksum command reads the checksum in the specified address range. silicon signature command reads silicon signature information. system setting, control security setting command disables the block erase, chip erase, program, read commands, and rewriting of the boot area. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 673 24.2.6 pin connection when performing on-board writing, mount a connector on t he target system to conne ct to the dedicated flash programmer. also, incorporate a function on-board to s witch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after rese t. therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, see 24.3.5 (1) flmd0 pin . figure 24-9. flmd0 pin connection example v850es/hj2 flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 ) (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 24-10. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/hj2 caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 674 table 24-4. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited (3) serial interface pin the following shows the pins used by each serial interface. table 24-5. pins used by serial interfaces serial interface pins used uarta0 txda0, rxda0 csib0 sob0, sib0, sckb0 csib0 + hs sob0, sib0, sckb0, pcm0 when connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash programmer (output) is connec ted to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 24-11. conflict of signals (serial interface input pin) v850es/hj2 input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 675 (b) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 24-12. malfunction of other device v850es/hj2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/hj2 outputs affects the other device, isolate the signal on the other device side. v850es/hj2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 676 (4) reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signal s occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 24-13. conflict of signals (reset pin) v850es/hj2 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. (5) port pins (including nmi) when the system shifts to the flash memory programmi ng mode, all the pins that are not used for flash memory programming are in the same st atus as that immediately after rese t. if the external device connected to each port does not recognize the st atus of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, and xt2 in the same st atus as that in the normal operation mode. during flash memory programming, input a low level to the drst pin or leave it open. do not input a high level. (7) power supply supply the same power (v dd , v ss , ev dd , ev ss , bv dd , bv ss , av ref0 , av ss , regc) as in normal operation mode. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 677 24.2.7 recommended circuit example for writing figure 24-14 shows the recommended circuit example for writing. figure 24-14. procedure for manipulating flash memory v dd v ss reset sob0/txda0 sib0/rxda0 sckb0 flmd0 flmd1 regc v dd v ss reset sib0/rxda0 sob0/txda0 sckb0 flmd0 flmd1 v850es/hj2 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xx x y y y xxx xx xxxxxx xxxx xx x x y yy y s tat v e flashpro iv pull-down resistor (r flmd1 ) 5 v capacitor (capacitance = 4.7 pf) chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 678 24.3 rewriting by self programming 24.3.1 overview the v850es/hj2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. by using this interface and a self programming library that is used to rewrit e the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program c an be upgraded and constant data can be rewritten in the field. figure 24-15. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 679 24.3.2 features (1) secure self programming (boot swap function) the v850es/hj2 supports a boot swap function that can exchange the physical memory of blocks 0 and 1 with the physical memory of blocks 2 a nd 3. by writing the start program to be rewritten to blocks 2 and 3 in advance and then swapping the physical memory, the ent ire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 and 1. figure 24-16. rewriting entire memory area (boot swap) block 0 block 1 block 2 block 3 block 4 : last block block 0 block 1 block 2 block 3 block 4 : last block block 0 block 1 block 2 block 3 block 4 : last block boot swap rewriting blocks 2 and 3 (2) interrupt support instructions cannot be fetched from the flash memory dur ing self programming. conventionally, a user handler written to the flash memory could not be used even if an interrupt occurred. therefore, in the v850es/hj2, to use an interrupt during self programming, processing transits to the specific address note in the internal ram. allocate the jump instru ction that transits processi ng to the user interrupt servicing at the specific address note in the internal ram. note nmi interrupt: start address of internal ram maskable interrupt: start address of internal ram + 4 addresses chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 680 24.3.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 24-17. standard self programming flow flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swap processing note 2 flash environment end processing flash memory manipulation end of processing all blocks end? ? disable accessing flash area ? disable setting of stop mode ? disable stopping clock yes no notes 1. if a security setting is not performed, flash in formation setting processing does not have to be executed. 2. if boot swap is not used, flash information setting processing and boot swap processing do not have to be executed. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 681 24.3.4 flash functions table 24-6. flash function list function name outline support flashenv initialization of flash control macro flashblockerase erasure of specified one block flashwordwrite writing from specified address flashblockiverify internal verification of specified one block flashblockblankcheck blank check of specified one block flashflmdcheck check of flmd pin flashstatuscheck status check of o peration specified immediately before flashgetinfo reading of flash information flashsetinfo setting of flash information flashbootswap swapping of boot area flashwordread data read from specified address flashsetuserhandler user interrup t handler registration function 24.3.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when re set is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is exec uted. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self programming m ode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 24-18. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v when reset is released. chapter 24 flash memory preliminary user?s manual u17717ej2v0ud 682 24.3.6 internal resources used the following table lists the internal resources used for se lf programming. these internal resources can also be used freely for purposes ot her than self programming. table 24-7. internal resources used resource name description stack area (user stack + (tbd) bytes) an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code ((tbd) bytes) program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as a user application. calls flash functions. maskable interrupt can be used in user application execut ion status or self programming status. to use this interrupt in the self-programming status, since the processing transits to the address of the internal ram start address + 4 addresses, allocate the jump instruction that transits the processing to the user interrupt servicing at the address of the internal ram start address + 4 addresses in advance. nmi interrupt can be used in user application execution status or self programming status. to use this interrupt in the self-programming status, since the processing transits to the address of the internal ram start address, allocate the jump instruction that transits the processing to the user interrupt servicing at the internal ram start address in advance. preliminary user?s manual u17717ej2v0ud 683 chapter 25 option byte function the option byte is stored in address 0 00007ah of the internal flash memory (internal rom area) as 8-bit data. when writing a program to the v850es/hj2, be sure to se t the option data corresponding to the following option in the program at address 000007ah as default data. the data in this area cannot be re written during program execution. opb7 opb7 0 1 crystal resonator mode rc oscillator mode opb6 opb6 0 1 ?? ?? opb1 opb0 address: 0000007ah subclock operation mode setting opb0 0 1 stopping enabled stopping disabled stopping internal oscillator enable/disable opb1 0 1 operating clock (f x /f r ) selectable intwdt2 mode/wdtres mode selectable fixed to internal oscillation clock (f r ) fixed to wdtres mode watchdog timer 2 mode setting preliminary user?s manual u17717ej2v0ud 684 chapter 26 on-chip debug function the v850es/hj2 has an on-chip debug f unction that uses the jtag (joint test action group) interface (drst, dck, dms, ddi, and ddo pins) and that can be used via an on-chip debug emulator (minicube ? ). 26.1 features { hardware break function: 2 points { software break function: 4 points { real-time ram monitor function: memory cont ents can be read during program execution. { dynamic memory modification function (dmm function): ram contents can be rewritten during program execution. { mask function: reset, nmi, hldrq, wait { rom security function: 10-byte id code authentication caution the following func tions are not supported. ? trace function ? event function ? debug interrupt inte rface function (dbint) chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 685 26.2 connection circuit example minicube v850es/hj2 vdd dck dms ddi ddo drst reset flmd0 gnd ev dd dck dms ddi ddo drst note 2 reset flmd0 note 3 flmd1/pdl5 ev ss note 1 status target power notes 1. example of pin connection wh en minicube is not connected 2. a pull-down resistor is provided on chip. 3. for flash memory rewriting chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 686 26.3 interface signals the interface signals are described below. (1) drst this is a reset input signal for the on-chip debug un it. it is a negative-logic signal that asynchronously initializes the debug control unit. minicube raises the drst signal when it detects v dd of the target system after the integrated debugger is started, and starts the on-chip debug unit of the device. when the drst signal goes high, a reset signal is also generated in the cpu. when starting debugging by starti ng the integrated debugger, a cpu reset is always generated. (2) dck this is a clock input signal. it supplies a 20 mhz cl ock from minicube. in the on-chip debug unit, the dms and ddi signals are sampled at the rising edge of the dck signal, and the data ddo is output at its falling edge. (3) dms this is a transfer mode select signal. the transfer st atus in the debug unit changes depending on the level of the dms signal. (4) ddi this is a data input signal. it is sampled in the on-chip debug unit at the rising edge of dck. (5) ddo this is a data output signal. it is output from the on- chip debug unit at the falling edge of the dck signal. (6) ev dd this signal is used to detect vdd of the target system. if vdd from t he target system is not detected, the signals output from minicube (drst, dck, dms, ddi, flmd0, and reset) go into a high-impedance state. chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 687 (7) flmd0 the flash self programming function is used for the function to download data to the flash memory via the integrated debugger. during flash self programming, the flmd0 pin must be kept high. in addition, connect a pull-down resistor to the flmd0 pin. the flmd0 pin can be controlled in either of the following two ways. <1> to control from minicube connect the flmd0 signal of minicube to the flmd0 pin. in the normal mode, nothing is dr iven by minicube (high impedance). during a break, minicube raises the flmd0 pin to the high level when the download function of the integrated debugger is executed. <2> to control from port connect any port of the device to the flmd0 pin. the same port as the one used by the user program to realize the fl ash self programming function may be used. on the console of the integrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pin after executing the download function. for details, refer to the id850qb ver. 3.10 integrated de bugger operation user?s manual (u17435e) . (8) reset this is a system reset input pin. if the drst pin is made invalid by the value of the ocdm.ocdm0 bit set by the user program, on-chip debugging cannot be executed. t herefore, reset is effe cted by minicube, using the reset pin, to make the drs t pin valid (ini tialization). chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 688 26.4 register (1) on-chip debug m ode register (ocdm) the ocdm register is used to sele ct the normal operation mode or on-chip debug mode. this register is a special register and can be written only in a combination of specific sequences (see 3.4.7 special registers ). this register is also used to specify whether a pi n provided with an on-chip debug function is used as an on- chip debug pin or as an ordinary port/peripheral function pin. it also is used to disconnect the internal pull- down resistor of the p05 pin. the ocdm register can be written only while a low level is input to the p05 pin. this register can be read or written in 8-bit or 1-bit units. 0 ocdm0 0 1 operation mode ocdm 0 0 0 0 0 0 ocdm0 after reset: 01h note r/w address: fffff9fch when p05 pin is low: normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) when p05 pin is high: on-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the p05 pin. note the value of this register is 01 h after reset by the reset pin and is 00h after reset by power-on-clear circuit (poc). after reset by the wdtres2 signal, clock monitor (clm), or low-voltage detector (lvi), however, the value of the o cdm register is retained. cautions 1. when using the ddi, ddo, dck, and dms pins not as on-ch ip debug pins but as port pins after external reset, the foll owing actions must be taken. ? input a low level to the p05 pin. ? set the odcm0 bit. in this case, take the following actions. <1> clear the ocdm0 bit to 0. <2> fix the p05 pin to the lo w level until <1> is completed. 2. the p05 pin has an on-chip pull-down resistor. this resi stor is disconnected when the ocdm0 flag is cleared to 0. ocdm0 flag (1: pull-down on, 0: pull-down off) 10 to 100 k ? (30 k ? (typ.)) p05 chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 689 26.5 operation the on-chip debug function is made invalid under the conditions shown in the table below. when this function is not used, keep the drst pin low until the ocdm.ocdm0 flag is cleared to 0. ocdm0 flag drst pin 0 1 l invalid invalid h invalid valid remark l: low-level input h: high-level input figure 26-1. timing when on-chip debug function is not used low-level input after ocdm0 bit is cleared, high level can be input/output. clearing ocdm0 bit releasing reset reset ocdm0 p05/intp2/drst chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 690 26.6 rom security function 26.6.1 security id the flash memory versions of the v850es/hj2 perform authentication usi ng a 10-byte id code to prevent the contents of the flash memory from being read by an unaut horized person during on-chip debugging by the on-chip debug emulator. set the id code in the 10-byte on-chip flash memory area from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading fl ash memory and using the on-chip debug emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the on-chip debug emulator enable flag. (0: disable, 1: enable) ? when the on-chip debug emulator is started, the debugger requests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the on-chip debug emul ator enable flag is 0, even if the id codes match. 0000079h 0000070h 0000000h security id (10 bytes) caution when the data in the flash memory has been deleted, all the bits are set to 1. chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 691 26.6.2 setting the following shows how to set the id code as shown in table 26-1. when the id code is set as shown in table 26-1, the id code input in the configuration dialog box of the id850qb is ?123456789abcdef123d4? (not case-sensitive). table 26-1. id code address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 the id code can be specified for the devic e file that supports the ca850 ver. 2.60 or later and the security id by the pm+ linker option setting. chapter 26 on-chip debug function preliminary user?s manual u17717ej2v0ud 692 [program example (when usi ng ca850 ver. 2.60 or later)] #-------------------------------------- # securityid (continue ilgop handler) #-------------------------------------- .section "security_id" --interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xf1debc9a --4-7 byte code .hword 0xd423 --8-9 byte code remark add the above program exam ple to the startup files. 26.7 cautions (1) if a reset signal is input (from the target system or a reset signal from an internal reset source) during run (program execution), the br eak function may malfunction. (2) even if the reset signal is masked by the mask function, the i/o buffer (port pin) may be reset if a reset signal is input from a pin. (3) because a software breakpoint set in the internal flash me mory is realized by the rom correction function, it is made temporarily invalid by target reset or internal reset generated by watchdog timer 2. the breakpoint becomes valid again when a hardware break or forced br eak occurs, but a software break does not occur until then. (4) pin reset during a break is masked and the cpu and perip heral i/o are not reset. if pi n reset or internal reset is generated as soon as the flash memo ry is rewritten by dma or read by the ram monitor function while the user program is being executed, the cpu and peripheral i/o may not be correctly reset. (5) in the on-chip debug mode, the ddo pin is forcibly set to the high-level output. preliminary user?s manual u17717ej2v0ud 693 chapter 27 electrical specifications (target) 27.1 electrical specifications absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = bv dd ? 0.5 to +6.5 v bv dd v dd = ev dd = bv dd ? 0.5 to +6.5 v ev dd v dd = ev dd = bv dd ? 0.5 to +6.5 v av ref0 ? 0.5 to +6.5 v v ss v ss = ev ss = bv ss = av ss ? 0.5 to +0.5 v av ss v ss = ev ss = bv ss = av ss ? 0.5 to +0.5 v bv ss v ss = ev ss = bv ss = av ss ? 0.5 to +0.5 v supply voltage ev ss v ss = ev ss = bv ss = av ss ? 0.5 to +0.5 v v i1 p00 to p06, p10, p11, p30 to p39, p40 to p42, p50 to p55, p60 to p615, p80, p81, p90 to p915, reset, flmd0 ? 0.5 to ev dd + 0.5 note v v i2 pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15 ? 0.5 to bv dd + 0.5 note v input voltage v i3 x1, x2, xt1, xt2 ? 0.5 to v ro + 0.5 note v analog input voltage v ian p70 to p715, p120 to p127 ? 0.5 to av ref0 + 0.5 note v note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are ra ted values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. 3. when directly connecting to the external circuit the pin that becomes high impedance state, the timing must be designed such that the output conflict is avoided on the external circuit. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 694 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 4 ma p00 to p06, p10, p11, p30 to p39, p40 to p42, p50 to p55, p60 to p615, p80, p81, p90 to p915 total of all pins 50 ma per pin 4 ma p70 to p715, p120 to p127 total of all pins 20 ma per pin 4 ma output current, low i ol pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15 total of all pins 50 ma per pin ? 4 ma p00 to p06, p10, p11, p30 to p39, p40 to p42, p50 to p55, p60 to p615, p80, p81, p90 to p915 total of all pins ? 50 ma per pin ? 4 ma p70 to p715, p120 to p127 total of all pins ? 20 ma per pin ? 4 ma output current, high i oh pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15 total of all pins ? 50 ma normal operation mode operating ambient temperature t a flash memory programming mode ? 40 to +85 c storage temperature t stg ? 40 to +125 c cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc and gnd. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are ra ted values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. 3. when directly connecting to the external circuit the pin that becomes high impedance state, the timing must be designed such that the output conflict is avoided on the external circuit. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 695 27.2 capacitance (t a = 25 c, v dd = ev dd = av ref0 = bv dd = v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i/o capacitance c io f x = 1 mhz, unmeasured pins returned to 0 v. 10 pf 27.3 operating conditions (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit regc = 4.7 f, at operation with main clock 4 20 mhz regc = 4.7 f, at operation with subclock (crystal resonator) 32 35 khz internal system clock frequency f clk regc = 4.7 f, at operation with subclock (rc resonator) 12.5 note 2 27.5 note 2 khz note the internal system clock frequency is half the oscillation frequency. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 696 27.4 oscillator characteristics 27.4.1 main clock oscillator characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 4 5 mhz after reset release 2 16 /f x s after stop mode release 0.5 note 3 note 4 ms ceramic resonator oscillation stabilization time note 2 after idle2 mode release 0.35 note 3 note 4 ms oscillation frequency (f x ) note 1 4 5 mhz after reset release 2 16 /f x s after stop mode release 0.5 note 3 note 4 ms crystal resonator x2 x1 oscillation stabilization time note 2 after idle2 mode release 0.35 note 3 note 4 ms notes 1. indicates only oscillator characteristics. 2. time required to stabilize the crystal resona tor after reset or stop mode is released. 3. time required to stabilize access to the internal flash memory. 4. the value differs depending on the osts register settings. cautions 1. when using the main cl ock oscillator, wire as follows in the area enclosed by th e broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main clock is stopped and the subclock is operati ng, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 697 27.4.2 subclock oscillator characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator xt2 xt1 oscillation stabilization time note 2 10 s oscillation frequency (f xt ) notes 1, 4 r = 390 k ? 5% note 3 c = 47 pf 10% note 3 25 40 55 khz rc resonator xt2 xt1 oscillation stabilization time note 2 100 s notes 1. indicates only oscillator characterist ics. for the cpu operation clock, see 27.8 ac characteristics . 2. time required from when v dd reaches oscillation voltage range (min.: 3.5 v) to when the crystal resonator stabilizes. 3. to avoid an adverse effect from wiring capacitanc e, keep the wiring length as short as possible. 4. rc oscillation frequency is 40 khz (typ.). this clock is internally divided by 2. in the case of the rc resonator, the internal system clock frequency is half the oscillation frequency: min. = 12.5 khz, typ. = 20 khz, max. = 27.5 khz. cautions 1. when using the subclock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-amp litude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main clock oscillato r. particular care is therefore required with the wiring me thod when the subclock is used. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 698 27.4.3 pll characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 4 5 mhz output frequency f xx 16 20 mhz lock time t pll after v dd reaches min.: 3.5 v 800 s 27.4.4 internal oscill ator characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit output frequency f r 100 200 400 khz 27.5 voltage regulator characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd , v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency v dd 3.5 5.5 v output frequency v ro 2.5 v lock time t reg after v dd reaches min.: 3.5 v, c = 4.7 f 20% connected to regc pin 1 ms v dd 3.5 v v ro reset t reg chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 699 27.6 dc characteristics 27.6.1 i/o level (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 p30, p34, p36 to p38, p41, p63 to p69, p614, p615, p81, p98, p911 0.7ev dd ev dd v v ih2 p00 to p06, p10, p11, p31 to p33, p35, p39, p40, p42, p50 to p55, p60 to p62, p610 to p613, p80, p90 to p97, p99, p910, p912 to p915 0.8ev dd ev dd v v ih3 pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15 0.7bv dd bv dd v v ih4 p70 to p715, p120 to p127 0.7av ref0 av ref0 v input voltage, high v ih5 reset, flmd0 0.8ev dd ev dd v v il1 p30, p34, p36 to p38, p41, p63 to p69, p614, p615, p81, p98, p911 ev ss 0.3ev dd v v il2 p00 to p06, p10, p11, p31 to p33, p35, p39, p40, p42, p50 to p55, p60 to p62, p610 to p613, p80, p90 to p97, p99, p910, p912 to p915 ev ss 0.2ev dd v v il3 pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15 bv ss 0.3bv dd v v il4 p70 to p715, p120 to p127 av ss 0.3av ref0 v input voltage, low v il5 reset, flmd0 ev ss 0.2ev dd v remark unless specified otherwise, the characte ristics of alternate-function pins are the same as those of port pins. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 700 (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit i oh = ? 1.0 ma ev dd ? 1.0 ev dd v v oh1 p00 to p06, p10, p11, p30 to p39, p40 to p42, p50 to p55, p60 to p615, p80 to p81, p90 to p915 i oh = ? 0.1 ma ev dd ? 0.5 ev dd v i oh = ? 1.0 ma bv dd ? 1.0 bv dd v v oh2 pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15 i oh = ? 0.1 ma bv dd ? 0.5 bv dd v i oh = ? 1.0 ma av ref0 ? 1.0 av ref0 v output voltage, high note 1 v oh3 p70 to p715, p120 to p127 i oh = ? 0.1 ma av ref0 ? 0.5 av ref0 v v ol1 p00 to p06, p10, p11, p30 to p39, p40 to p42, p50 to p55, p60 to p615, p80, p81, p90 to p915 i ol = 10 ma 0 0.4 v v ol2 pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15 i ol = 1.0 ma 0 0.4 v output voltage, low note 1 v ol3 p70 to p715, p120 to p127 i ol = 1.0 ma 0 0.4 v pull-up resistor r 1 v i = 0 v 10 30 100 k ? pull-down resistor note 2 r 2 v i = v dd 10 30 100 k ? notes 1. the maximum value of the total of i oh /i ol is 20 ma/ ? 20 ma for each power supply (ev dd , bv dd , av ref0 ). 2. drst pin only remark unless specified otherwise, the characte ristics of alternate-function pins are the same as those of port pins. 27.6.2 pin leakage current (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit analog pin +2.0 input leakage current, high i lih1 v in = v dd other than analog pin +5.0 a analog pin ? 2.0 input leakage current, low i lil1 v in = 0 v other than analog pin ? 0.5 a analog pin +0.2 output leakage current, high i loh1 v o = v dd other than analog pin +5.0 a analog pin ? 0.2 output leakage current, low i lol1 v o = 0 v other than analog pin ? 5.0 a caution the value of the fmld0 pin is as follows. ? input leakage current, high: 2 a (max) ? input leakage current, low: ? 2 a (max) chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 701 27.6.3 supply current (1) pd70f3711, 70f3712 (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit all peripheral function operating 40 55 ma i dd1 normal operation mode f xx = 20 mhz (f x = 5 mhz) all peripheral function stopped 27 ma all peripheral function operating 25 35 ma i dd2 halt mode f xx = 20 mhz (f x = 5 mhz) all peripheral function stopped 14 ma i dd3 idle1 mode f xx = 5 mhz (f x = 5 mhz), pll off 0.6 0.9 ma i dd4 idle2 mode f xx = 5 mhz (f x = 5 mhz), pll off 0.25 0.7 ma crystal resonator (f xt = 32.768 khz) 200 400 a i dd5 subclock operation mode notes 2, 3 rc oscillator (f xt = 40 khz note 4 ) 200 400 a crystal resonator (f xt = 32.768 khz) 20 120 a i dd6 sub-idle mode notes 2, 3 rc oscillator (f xt = 40 khz note 4 ) 35 140 a poc stopped, internal oscillator stopped 7 50 a poc operating, internal oscillator stopped 10 55 a poc stopped, internal oscillator operating 15 65 a supply current note 1 i dd7 stop mode notes 2, 5 poc operating, internal oscillator operating 18 70 a notes 1. total current of v dd , ev dd , and bv dd (all ports stopped). the current of av ref0 and the port buffer current including the current flowing through the on-chi p pull-up/pull-down resistors are not included. 2. when the main clock oscillation is stopped. 3. poc operating, internal oscillator operating. 4. the rc oscillation frequency is 40 khz (typ.). this clock is internally divided by 2. 5. when the subclock oscillation is not used. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 702 (2) pd70f3709, 70f3710 (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit all peripheral function operating 30 45 ma i dd1 normal operation mode f xx = 20 mhz (f x = 5 mhz) all peripheral function stopped 22 ma all peripheral function operating 18 28 ma i dd2 halt mode f xx = 20 mhz (f x = 5 mhz) all peripheral function stopped 11 ma i dd3 idle1 mode f xx = 5 mhz (f x = 5 mhz), pll off 0.6 0.9 ma i dd4 idle2 mode f xx = 5 mhz (f x = 5 mhz), pll off 0.25 0.7 ma crystal resonator (f xt = 32.768 khz) 200 400 a i dd5 subclock operation mode notes 2, 3 rc resonator (f xt = 40 khz note 4 ) 200 400 a crystal resonator (f xt = 32.768 khz) 20 120 a i dd6 sub-idle mode notes 2, 3 rc resonator (f xt = 40 khz note 4 ) 35 140 a poc stopped, internal oscillator stopped 7 50 a poc operating, internal oscillator stopped 10 55 a poc stopped, internal oscillator operating 15 65 a supply current note 1 i dd7 stop mode notes 2, 5 poc operating, internal oscillator operating 18 70 a notes 1. total current of v dd , ev dd , and bv dd (all ports stopped). the current of av ref0 and the port buffer current including the current flowing through the on-chi p pull-up/pull-down resistors are not included. 2. when the main clock oscillation is stopped. 3. poc operating, internal oscillator operating. 4. the rc oscillation frequency is 40 khz (typ.). this clock is internally divided by 2. 5. when the subclock oscillation is not used. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 703 27.7 data retention characteristics stop mode (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 1.9 v to 5.5 v, v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr in stop mode 1.9 5.5 v data retention current i dddr v dddr = 2.0 v 6 45 a supply voltage rise time t rvd 1 s supply voltage fall time t fvd 1 s supply voltage retention time t hvd after stop mode release 0 ms stop release signal input time t drel after v dd reaches min.: 3.5 v 0 s data retention input voltage, high v ihdr all input ports 0.9v dddr v dddr v data retention input voltage, low v ildr all input ports 0 0.1v dddr v caution shifting to stop mode and restoring from stop mode must be performed within the rated operating range. t drel t hvd t fvd t rvd stop release signal input stop mode setting v dddr v ihdr v ihdr v ildr v dd /ev dd /bv dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit (min.) chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 704 27.8 ac characteristics (1) ac test input measurement points (v dd , av ref0 , ev dd , bv dd ) v dd v ss v ih (min.) v il (max.) v ih (min.) v il (max.) measurement points (2) ac test output measurement points v oh (min.) v ol (max.) v oh (min.) v ol (max.) measurement points (3) load conditions dut (device under measurement) c l = 50 pf caution if the load cap acitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 705 27.8.1 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk 50 ns 80 s high-level width t wkh t cyk /2 ? 15 ns low-level width t wkl t cyk /2 ? 15 ns rise time t kr 15 ns fall time t kf 15 ns clock timing clkout (output) t cyk t wkh t wkl t kr t kf chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 706 27.8.2 bus timing (1) clkout asynchronous (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast (0.5 + t asw ) ? 20 ns address hold time (from astb ) t hsta (0.5 + t ahw ) ? 15 ns delay time from rd to address float t frda 16 ns data input setup time from address t said (2 + n + t asw + t ahw )t ? 40 ns data input setup time from rd t srdid (1 + n)t ? 30 ns delay time from astb to rd, wrm t dstrdwr (0.5 + t ahw )t ? 15 ns data input hold time (from rd ) t hrdid 0 ns address output time from rd t drda (1 + i )t ? 15 ns delay time from rd, wrm to astb t drdwrst 0.5t ? 15 ns delay time from rd to astb t drdst (1.5 + i + t asw )t ? 15 ns rd, wrm low-level width t wrdwrl (1 + n)t ? 20 ns astb high-level width t wsth (1 + i + t asw )t ? 15 ns data output time from wrm t dwrod 15 ns data output setup time (to wrm ) t sodwr (1 + n)t ? 25 ns data output hold time (from wrm ) t hwrod t ? 15 ns t sawt1 (1.5 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 n 1 (1.5 + n + t asw + t ahw )t ? 45 ns t hawt1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 n 1 (1.5 + n + t asw + t ahw )t ns t sstwt1 (1 + t ahw )t ? 35 ns wait setup time (to astb ) t sstwt2 n 1 (1 + n + t ahw )t ? 35 ns t hstwt1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 n 1 (1 + n + t ahw )t ns hldrq high-level width t whqh t + 10 ns hldak low-level width t whal t ? 20 ns delay time from hldak to bus output t dhac ?3 ns delay time from hldrq to hldak t dhqha1 (2n + 7.5)t + 25 ns delay time from hldrq to hldak t dhqha2 0.5t 1.5t + 35 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: number of idle states inserted after a read cycle (0 or 1). 5. the values in the above specific ations are values for when clocks with a 1:1 duty ratio are input from x1. 6. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 707 (2) clkout synchronous (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka 0 24 ns delay time from clkout to address float t fka 0 24 ns delay time from clkout to astb t dkst ? 12 +12 ns delay time from clkout to rd, wrm t dkrdwr ? 5 14 ns data input setup time (to clkout ) t sidk 20 ns data input hold time (from clkout ) t hkid 5 ns data output delay time from clkout t dkod 22 ns wait setup time (to clkout ) t swtk 30 ns wait hold time (from clkout ) t hkwt 5 ns hldrq setup time (to clkout ) t shqk 30 ns hldrq hold time (from clkout ) t hkhq 5 ns delay time from clkout to hldak t dkha 24 ns delay time from clkout to bus float t dkf 25 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 708 read cycle (clkout sync hronous/asynchronous, 1 wait) clkout (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 address hi-z t dka t dkst t sast t hsta t wsth t fka t said t dkst t hrdid t drdwrst t dkrdwr t srdid t dstrdwr t sstwt1 t swtk t hstwt1 t sstwt2 t hstwt2 t sawt1 t hawt1 t sawt2 t hawt2 t swtk t hkwt t hkwt t wrdwrl t drda t drdst t sidk t hkid t dkrdwr t frda data remark wr0 and wr1 are high level. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 709 write cycle (clkout sync hronous/asynchronous, 1 wait) clkout (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 data address t dka t dkst t dkrdwr t dkrdwr t hkwt t hkwt t swtk t sstwt1 t hstwt1 t sstwt2 t hstwt2 t sawt1 t hawt1 t sawt2 t hawt2 t sast t wsth t drdwrst t hwrod t soder t wrdwrl t dstrdwr t dwrod t dkst t dkod t hsta t swtk remark rd is high level. chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 710 bus hold clkout (output) hldrq (input) hldak (output) ad0 to ad15 (i/o) astb (output) rd (output), wr0 (output), wr1 (output) th th th ti hi-z hi-z data hi-z t shqk t shqk t dkf t dkf t hkhq t whqh t dhqha2 t whal t dhac t dhqha1 t dkha chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 711 27.9 basic operation (1) reset, interrupt timing (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit reset low-level width t wrsl 500 ns nmi high-level width t wnih analog noise elimination 500 ns nmi low-level width t wnil analog noise elimination 500 ns analog noise elimination (n = 0 to 14) 500 ns intpn note 1 high-level width t with digital noise elimination (n = 3) note 2 ns analog noise elimination (n = 0 to 14) 500 ns intpn note 1 low-level width t witl digital noise elimination (n = 3) note 2 ns notes 1. the same value as the intp0/p03 pi n applies in the case of the adtr g pin. the same value as the intp2/p05 pin applies in the case of the drst pin. 2. 2t samp + 20 or 3t samp + 20 t samp : sampling clock for noise elimination reset/interrupt t reg t wnih t wrsl v dd reset (input) nmi (input) intpn (input) t wnil t with t witl remark n = 0 to 14 chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 712 (2) key interrupt timing (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit krn input high-level width t wkrh 500 ns krn input low-level width t wkrl analog noise elimination (n = 0 to 7) 500 ns t wkrh krn (input) t wkrl remark n = 0 to 7 (3) timer input timing (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit tin high-level width t tih note 2 ns tin low-level width t til tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tiq00 to tiq03, tiq10 to tiq13, tiq20 to tiq23 note 1 note 2 ns notes 1. noise on the tip00, tip10, tip20, tip30, tiq00, tiq10, and tiq20 pins c an be eliminated only when a capture signal is input. the noise cannot be eliminated when an external trigger signal or an external event counter signal is input. 2. 2t samp + 20 or 3t samp + 20 t samp : sampling clock for noise elimination t tih tin (input) t til remark tin: tip00, tip01, tip10 tip11, tip20, tip21, tip30, tip31, t iq00 to tiq03, tiq10 to tiq13, tiq20 to tiq23 chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 713 (4) csib timing (a) master mode (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle time t kcyn 125 ns sckbn high-level width t khn t kcyn /2 ? 15 ns sckbn low-level width t kln t kcyn /2 ? 15 ns sibn setup time (to sckbn ) t sikn 30 ns sibn hold time (from sckbn ) t ksin 25 ns output delay time from sckbn to sobn t kson 25 ns remark n = 0 to 2 (b) slave mode (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle time t kcyn 200 ns sckbn high-level width t khn 90 ns sckbn low-level width t kln 90 ns sibn setup time (to sckbn ) t sikn 50 ns sibn hold time (from sckbn ) t ksin 50 ns output delay time from sckbn to sobn t kson 50 ns remark n = 0 to 2 chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 714 t kln t sikn t ksin t kson t kcyn t khn sobn (output) input data output data sibn (input) sckbn (i/o) hi-z remark n = 0 to 2 (5) uarta timing (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit communication rate 312.5 kbps asck0 cycle time 10 mhz (6) a/d converter (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 4.0 av ref0 5.5 v 0.15 0.3 %fsr conversion time t conv 3.1 16 s analog input voltage v ian av ss av ref0 v when using a/d converter 5 10 ma av ref0 current i aref0 when not using a/d converter 1 10 a note excluding quantization error ( 0.05 %fsr). indicates the ratio to the full-scale value (%fsr). remark fsr: full scale range chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 715 (7) poc circuit characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit detection voltage v poc0 3.5 3.7 3.9 v power supply startup time t pth v dd = 0 v 3.5 v 0.002 ms response delay time 1 note 1 t pthd after v dd reaches 3.9 v on power application 3.0 ms response delay time 2 note 2 t pd after v dd drops below 3.5 v on power drop 1 ms minimum v dd width t pw 0.2 ms notes 1. the time required to release a reset a fter the detection voltage is detected. 2. the time required to output a reset a fter the detection voltage is detected. t pth t pthd v dd detection voltage (max.) detection voltage (typ.) detection voltage (min.) time t pw t pd t pthd chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 716 (8) lvi circuit characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v lvi0 4.2 4.4 4.6 v detection voltage v lvi1 4.0 4.2 4.4 v response time note 1 t ld after v dd reaches v lvi0 /v lvi1 (max.) or drops below v lvi0 /v lvi1 (min.) 0.2 2 ms minimum v dd width t lw 0.2 ms reference voltage stabilization wait time note 2 t lwait after v dd reaches 3.5 v or lvion bit (lvim.bit7) changes from 0 to 1 0.1 0.2 ms notes 1. the time required to output an interrupt/r eset after the detection voltage is detected. 2. unnecessary when the poc function is used. t lwait lvion bit = 0 1 v dd detection voltage (max.) detection voltage (typ.) detection voltage (min.) time t lw t ld t ld chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 717 (9) ram retention flag characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit detection voltage v ramh 1.9 2.0 2.1 v supply voltage rise time t ramhth v dd = 0 v 3.5 v 0.002 1800 ms response time note t ramhd after the supply voltage reaches the detection voltage (max.) 0.2 2.0 ms minimum v dd width t ramhw 0.2 ms note time required to set the ramf bit a fter the detection volt age is detected. t ramhd v dd detection voltage (max.) detection voltage (typ.) detection voltage (min.) operating voltage (min.) time t ramhw t ramhth t ramhd chapter 27 electrical specifications (target) preliminary user?s manual u17717ej2v0ud 718 27.10 flash memory programming characteristics (1) basic characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit operating frequency f cpu 4 20 mhz supply voltage v dd 3.5 5.5 v number of writes c wrt note 100 times input voltage, high v ih flmd0 0.8ev dd ev dd v input voltage, low v il flmd0 ev ss 0.2ev ss v write time + erase time t iwrt + t erase tbd s programming temperature t prg ? 40 +85 c note when writing initially to shipped products, it is counted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites (2) serial write operation characteristics (t a = ? 40 to +85 c, v dd = ev dd = bv dd = 3.5 v to 5.5 v, 4.0 v av ref0 5.5 v, v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit flmd0 setup time from reset t rfcf 70536/f x s count execution time t count 3 ms flmd0 high-level width t ch 10 100 s flmd0 low-level width t cl 10 100 s flmd0 rise time t r 50 ns flmd0 fall time t f 50 ns l v ss v dd reset flmd0 flmd1 v ss v dd v ss v dd t count t rfcf t cl t f t r t ch preliminary user?s manual u17717ej2v0ud 719 chapter 28 package drawing 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b preliminary user?s manual u17717ej2v0ud 720 appendix a register index (1/11) symbol name unit page ada0cr0 a/d conversion result register 0 adc 466 ada0cr0h a/d conversion result register 0h adc 466 ada0cr1 a/d conversion result register 1 adc 466 ada0cr1h a/d conversion result register 1h adc 466 ada0cr10 a/d conversion result register 10 adc 466 ada0cr10h a/d conversion result register 10h adc 466 ada0cr11 a/d conversion result register 11 adc 466 ada0cr11h a/d conversion result register 11h adc 466 ada0cr12 a/d conversion result register 12 adc 466 ada0cr12h a/d conversion result register 12h adc 466 ada0cr13 a/d conversion result register 13 adc 466 ada0cr13h a/d conversion result register 13h adc 466 ada0cr14 a/d conversion result register 14 adc 466 ada0cr14h a/d conversion result register 14h adc 466 ada0cr15 a/d conversion result register 15 adc 466 ada0cr15h a/d conversion result register 15h adc 466 ada0cr16 a/d conversion result register 16 adc 466 ada0cr16h a/d conversion result register 16h adc 466 ada0cr17 a/d conversion result register 17 adc 466 ada0cr17h a/d conversion result register 17h adc 466 ada0cr18 a/d conversion result register 18 adc 466 ada0cr18h a/d conversion result register 18h adc 466 ada0cr19 a/d conversion result register 19 adc 466 ada0cr19h a/d conversion result register 19h adc 466 ada0cr2 a/d conversion result register 2 adc 466 ada0cr2h a/d conversion result register 2h adc 466 ada0cr20 a/d conversion result register 20 adc 466 ada0cr20h a/d conversion result register 20h adc 466 ada0cr21 a/d conversion result register 21 adc 466 ada0cr21h a/d conversion result register 21h adc 466 ada0cr22 a/d conversion result register 22 adc 466 ada0cr22h a/d conversion result register 22h adc 466 ada0cr23 a/d conversion result register 23 adc 466 ada0cr23h a/d conversion result register 23h adc 466 ada0cr3 a/d conversion result register 3 adc 466 ada0cr3h a/d conversion result register 3h adc 466 ada0cr4 a/d conversion result register 4 adc 466 ada0cr4h a/d conversion result register 4h adc 466 ada0cr5 a/d conversion result register 5 adc 466 appendix a register index preliminary user?s manual u17717ej2v0ud 721 (2/11) symbol name unit page ada0cr5h a/d conversion result register 5h adc 466 ada0cr6 a/d conversion result register 6 adc 466 ada0cr6h a/d conversion result register 6h adc 466 ada0cr7 a/d conversion result register 7 adc 466 ada0cr7h a/d conversion result register 7h adc 466 ada0cr8 a/d conversion result register 8 adc 466 ada0cr8h a/d conversion result register 8h adc 466 ada0cr9 a/d conversion result register 9 adc 466 ada0cr9h a/d conversion result register 9h adc 466 ada0m0 a/d converter mode register 0 adc 461 ada0m1 a/d converter mode register 1 adc 463 ada0m2 a/d converter mode register 2 adc 464 ada0pfm power-fail compare mode register adc 468 ada0pft power-fail compare threshold value register adc 468 ada0s a/d converter channel specification register 0 adc 465 adic interrupt control register intc 594 awc address wait control register bcu 209 bcc bus cycle control register bcu 210 bsc bus size configuration register bus bcu 199 cb0ctl0 csib0 control register 0 csi 526 cb0ctl1 csib0 control register 1 csi 529 cb0ctl2 csib0 control register 2 csi 530 cb0ric interrupt control register intc 594 cb0rx csib0 receive data register csi 525 cb0rxl csib0 receive data register l csi 525 cb0str csib0 status register csi 532 cb0tic interrupt control register intc 594 cb0tx csib0 transmit data register csi 525 cb0txl csib0 transmit data register l csi 525 cb1ctl0 csib1 control register 0 csi 526 cb1ctl1 csib1 control register 1 csi 529 cb1ctl2 csib1 control register 2 csi 530 cb1ric interrupt control register intc 594 cb1rx csib1 receive data register csi 525 cb1rxl csib1 receive data register l csi 525 cb1str csib1 status register csi 532 cb1tic interrupt control register intc 594 cb1tx csib1 transmit data register csi 525 cb1txl csib1 transmit data register l csi 525 cb2ctl0 csib2 control register 0 csi 526 cb2ctl1 csib2 control register 1 csi 529 cb2ctl2 csib2 control register 2 csi 530 cb2ric interrupt control register intc 595 appendix a register index preliminary user?s manual u17717ej2v0ud 722 (3/11) symbol name unit page cb2rx csib2 receive data register csi 525 cb2rxl csib2 receive data register l csi 525 cb2str csib2 status register csi 532 cb2tic interrupt control register intc 595 cb2tx csib2 transmit data register csi 525 cb2txl csib2 transmit data register l csi 525 ccls cpu operation clock status register cg 224 clm clock monitor mode register clm 646 ctbp call base pointer cpu 56 ctpc callt execution status saving register cpu 55 ctpsw callt execution status saving register cpu 55 dadc0 dma addressing control register 0 dma 558 dadc1 dma addressing control register 1 dma 558 dadc2 dma addressing control register 2 dma 558 dadc3 dma addressing control register 3 dma 558 dbc0 dma transfer count register 0 dma 557 dbc1 dma transfer count register 1 dma 557 dbc2 dma transfer count register 2 dma 557 dbc3 dma transfer count register 3 dma 557 dbpc exception/debug trap status saving register cpu 56 dbpsw exception/debug trap status saving register cpu 56 dchc0 dma channel control register 0 dma 559 dchc1 dma channel control register 1 dma 559 dchc2 dma channel control register 2 dma 559 dchc3 dma channel control register 3 dma 559 dda0h dma destination address register 0h dma 556 dda0l dma destination address register 0l dma 556 dda1h dma destination address register 1h dma 556 dda1l dma destination address register 1l dma 556 dda2h dma destination address register 2h dma 556 dda2l dma destination address register 2l dma 556 dda3h dma destination address register 3h dma 556 dda3l dma destination address register 3l dma 556 dmaic0 interrupt control register intc 595 dmaic1 interrupt control register intc 595 dmaic2 interrupt control register intc 595 dmaic3 interrupt control register intc 595 dsa0h dma source address register 0h dma 555 dsa0l dma source address register 0l dma 555 dsa1h dma source address register 1h dma 555 dsa1l dma source address register 1l dma 555 dsa2h dma source address register 2h dma 555 dsa2l dma source address register 2l dma 555 appendix a register index preliminary user?s manual u17717ej2v0ud 723 (4/11) symbol name unit page dsa3h dma source address register 3h dma 555 dsa3l dma source address register 3l dma 555 dtfr0 dma trigger factor register 0 dma 560 dtfr1 dma trigger factor register 1 dma 560 dtfr2 dma trigger factor register 2 dma 560 dtfr3 dma trigger factor register 3 dma 560 dwc0 data wait control register 0 bcu 207 ecr interrupt source register cpu 53 eipc interrupt status saving register cpu 52 eipsw interrupt status saving register cpu 52 fepc nmi status saving register cpu 53 fepsw nmi status saving register cpu 53 imr0 interrupt mask register 0 intc 595 imr0h interrupt mask register 0h intc 595 imr0l interrupt mask register 0l intc 595 imr1 interrupt mask register 1 intc 595 imr1h interrupt mask register 1h intc 595 imr1l interrupt mask register 1l intc 595 imr2 interrupt mask register 2 intc 595 imr2h interrupt mask register 2h intc 595 imr2l interrupt mask register 2l intc 595 imr3 interrupt mask register 3 intc 595 imr3h interrupt mask register 3h intc 595 imr3l interrupt mask register 3l intc 595 imr4 interrupt mask register 4 intc 595 imr4h interrupt mask register 4h intc 595 imr4l interrupt mask register 4l intc 595 intf0 external interrupt falling edge specification register 0 intc 95, 607 intf1 external interrupt falling edge specification register 1 intc 100, 608 intf3 external interrupt falling edge specification register 3 intc 106, 609 intf3h external interrupt falling edge specification register 3h intc 106, 609 intf3l external interrupt falling edge specification register 3l intc 106, 609 intf6l external interrupt falling edge specification register 6l intc 123, 610 intf8 external interrupt falling edge specification register 8 intc 130, 611 intf9h external interrupt falling edge specification register 9h intc 140, 612 intr0 external interrupt rising edge specification register 0 intc 95, 607 intr1 external interrupt rising edge specification register 1 intc 100, 608 intr3 external interrupt rising edge specification register 3 intc 107, 609 intr3h external interrupt rising edge specification register 3h intc 107, 609 intr3l external interrupt rising edge specification register 3l intc 107, 609 intr6l external interrupt rising edge specification register 6l intc 124, 610 intr8 external interrupt rising edge specification register 8 intc 130, 611 intr9h external interrupt rising edge specification register 9h intc 140, 612 appendix a register index preliminary user?s manual u17717ej2v0ud 724 (5/11) symbol name unit page ispr in-service priority register intc 597 kric interrupt control register intc 594 krm key return mode register kr 618 lockr lock register cg 227 lviic interrupt control register intc 594 lvim low-voltage detection register lvi 653 lvis low-voltage detection level select register lvi 654 nfc noise elimination control register intc 613 ocdm on-chip debug mode register debug 688 osts oscillation stabilization time select register wdt 623 p0 port 0 port 92 p00nfc tip00 pin noise elimination control register timer 247 p01nfc tip01 pin noise elimination control register timer 247 p1 port 1 port 98 p10nfc tip10 pin noise elimination control register timer 247 p11nfc tip11 pin noise elimination control register timer 247 p12 port 12 port 143 p20nfc tip20 pin noise elimination control register timer 247 p21nfc tip21 pin noise elimination control register timer 247 p3 port 3 port 102 p30nfc tip30 pin noise elimination control register timer 247 p31nfc tip31 pin noise elimination control register timer 247 p3h port 3h port 102 p3l port 3l port 102 p4 port 4 port 109 p5 port 5 port 112 p6 port 6 port 118 p6h port 6h port 118 p6l port 6l port 118 p7h port 7h port 126 p7l port 7l port 126 p8 port 8 port 128 p9 port 9 port 132 p9h port 9h port 132 p9l port 9l port 132 pc program counter cpu 50 pcc processor clock control register cg 220 pcd port cd port 145 pclm programmable clock mode register cg 229 pcm port cm port 147 pcs port cs port 150 pct port ct port 153 pdl port dl port 156 pdlh port dlh port 156 appendix a register index preliminary user?s manual u17717ej2v0ud 725 (6/11) symbol name unit page pdll port dll port 156 pemu1 peripheral emulation register 1 lvi 659 pfc0 port function control register 0 port 94 pfc3l port function control register 3l port 104 pfc5 port function control register 5 port 114 pfc6 port function control register 6 port 121 pfc6h port function control register 6h port 121 pfc6l port function control register 6l port 121 pfc9 port function control register 9 port 135 pfc9h port function control register 9h port 135 pfc9l port function control register 9l port 135 pfce3l port function control expansion register 3l port 105 pfce5 port function control expansion register 5 port 114 pfce9 port function control expansion register 9 port 136 pfce9h port function control expansion register 9h port 136 pfce9l port function control expansion register 9l port 136 pic0 interrupt control register intc 594 pic1 interrupt control register intc 594 pic10 interrupt control register intc 594 pic11 interrupt control register intc 595 pic12 interrupt control register intc 595 pic13 interrupt control register intc 595 pic14 interrupt control register intc 595 pic2 interrupt control register intc 594 pic3 interrupt control register intc 594 pic4 interrupt control register intc 594 pic5 interrupt control register intc 594 pic6 interrupt control register intc 594 pic7 interrupt control register intc 594 pic8 interrupt control register intc 594 pic9 interrupt control register intc 594 pllctl pll control register cg 226 plls pll lockup time specification register cg 228 pm0 port mode register 0 port 92 pm1 port mode register 1 port 98 pm12 port mode register 12 port 143 pm3 port mode register 3 port 102 pm3h port mode register 3h port 102 pm3l port mode register 3l port 102 pm4 port mode register 4 port 109 pm5 port mode register 5 port 112 pm6 port mode register 6 port 118 pm6h port mode register 6h port 118 appendix a register index preliminary user?s manual u17717ej2v0ud 726 (7/11) symbol name unit page pm6l port mode register 6l port 118 pm7h port mode register 7h port 126 pm7l port mode register 7l port 126 pm8 port mode register 8 port 128 pm9 port mode register 9 port 132 pm9h port mode register 9h port 132 pm9l port mode register 9l port 132 pmc0 port mode control register 0 port 93 pmc1 port mode control register 1 port 99 pmc3 port mode control register 3 port 103 pmc3h port mode control register 3h port 103 pmc3l port mode control register 3l port 103 pmc4 port mode control register 4 port 110 pmc5 port mode control register 5 port 113 pmc6 port mode control register 6 port 119 pmc6h port mode control register 6h port 119 pmc6l port mode control register 6l port 119 pmc8 port mode control register 8 port 129 pmc9 port mode control register 9 port 133 pmc9h port mode control register 9h port 133 pmc9l port mode control register 9l port 133 pmccm port mode control register cm port 148 pmccs port mode control register cs port 151 pmcct port mode control register ct port 154 pmcd port mode register cd port 145 pmcdl port mode control register dl port 157 pmcdlh port mode control register dlh port 157 pmcdll port mode control register dll port 157 pmcm port mode register cm port 147 pmcs port mode register cs port 150 pmct port mode register ct port 153 pmdl port mode register dl port 156 pmdlh port mode register dlh port 156 pmdll port mode register dll port 156 prcmd command register cpu 82 prscm0 prescaler compare register 0 wt 445, 551 prsm0 prescaler mode register 0 wt 444, 550 psc power save control register cg 621 psmr power save mode register cg 622 psw program status word cpu 54 pu0 pull-up resistor option register 0 port 94 pu1 pull-up resistor option register 1 port 99 pu3 pull-up resistor option register 3 port 106 appendix a register index preliminary user?s manual u17717ej2v0ud 727 (8/11) symbol name unit page pu3h pull-up resistor option register 3h port 106 pu3l pull-up resistor option register 3l port 106 pu4 pull-up resistor option register 4 port 110 pu5 pull-up resistor option register 5 port 116 pu6 pull-up resistor option register 6 port 123 pu6h pull-up resistor option register 6h port 123 pu6l pull-up resistor option register 6l port 123 pu8 pull-up resistor option register 8 port 129 pu9 pull-up resistor option register 9 port 140 pu9h pull-up resistor option register 9h port 140 pu9l pull-up resistor option register 9l port 140 q00nfc tiq00 pin noise elimination control register timer 347 q01nfc tiq01 pin noise elimination control register timer 347 q02nfc tiq02 pin noise elimination control register timer 347 q03nfc tiq03 pin noise elimination control register timer 347 q10nfc tiq10 pin noise elimination control register timer 347 q11nfc tiq11 pin noise elimination control register timer 347 q12nfc tiq12 pin noise elimination control register timer 347 q13nfc tiq13 pin noise elimination control register timer 347 q20nfc tiq20 pin noise elimination control register timer 347 q21nfc tiq21 pin noise elimination control register timer 347 q22nfc tiq22 pin noise elimination control register timer 347 q23nfc tiq23 pin noise elimination control register timer 347 r0 to r31 general-purpose register cpu 50 rams internal ram data status register cg 654 rcm internal oscillation mode register cg 224 resf reset source flag register cg 640 selcnt0 selector operation control register 0 timer 324 sys system status register cpu 83 tm0cmp0 tmm0 compare register 0 timer 434 tm0ctl0 tmm0 control register 0 timer 435 tm0eqic0 interrupt control register intc 594 tp0ccic0 interrupt control register intc 594 tp0ccic1 interrupt control register intc 594 tp0ccr0 tmp0 capture/compare register 0 timer 242 tp0ccr1 tmp0 capture/compare register 1 timer 244 tp0cnt tmp0 counter read buffer register timer 246 tp0ctl0 tmp0 control register 0 timer 235 tp0ctl1 tmp0 control register 1 timer 236 tp0ioc0 tmp0 i/o control register 0 timer 238 tp0ioc1 tmp0 i/o control register 1 timer 239 tp0ioc2 tmp0 i/o control register 2 timer 240 tp0opt0 tmp0 option register 0 timer 241 appendix a register index preliminary user?s manual u17717ej2v0ud 728 (9/11) symbol name unit page tp0ovic interrupt control register intc 594 tp1ccic0 interrupt control register intc 594 tp1ccic1 interrupt control register intc 594 tp1ccr0 tmp1 capture/compare register 0 timer 242 tp1ccr1 tmp1 capture/compare register 1 timer 244 tp1cnt tmp1 counter read buffer register timer 246 tp1ctl0 tmp1 control register 0 timer 235 tp1ctl1 tmp1 control register 1 timer 236 tp1ioc0 tmp1 i/o control register 0 timer 238 tp1ioc1 tmp1 i/o control register 1 timer 239 tp1ioc2 tmp1 i/o control register 2 timer 240 tp1opt0 tmp1 option register 0 timer 241 tp1ovic interrupt control register intc 594 tp2ccic0 interrupt control register intc 594 tp2ccic1 interrupt control register intc 594 tp2ccr0 tmp2 capture/compare register 0 timer 242 tp2ccr1 tmp2 capture/compare register 1 timer 244 tp2cnt tmp2 counter read buffer register timer 246 tp2ctl0 tmp2 control register 0 timer 235 tp2ctl1 tmp2 control register 1 timer 236 tp2ioc0 tmp2 i/o control register 0 timer 238 tp2ioc1 tmp2 i/o control register 1 timer 239 tp2ioc2 tmp2 i/o control register 2 timer 240 tp2opt0 tmp2 option register 0 timer 241 tp2ovic interrupt control register intc 594 tp3ccic0 interrupt control register intc 594 tp3ccic1 interrupt control register intc 594 tp3ccr0 tmp3 capture/compare register 0 timer 242 tp3ccr1 tmp3 capture/compare register 1 timer 244 tp3cnt tmp3 counter read buffer register timer 246 tp3ctl0 tmp3 control register 0 timer 235 tp3ctl1 tmp3 control register 1 timer 236 tp3ioc0 tmp3 i/o control register 0 timer 238 tp3ioc1 tmp3 i/o control register 1 timer 239 tp3ioc2 tmp3 i/o control register 2 timer 240 tp3opt0 tmp3 option register 0 timer 241 tp3ovic interrupt control register intc 594 tq0ccic0 interrupt control register intc 594 tq0ccic1 interrupt control register intc 594 tq0ccic2 interrupt control register intc 594 tq0ccic3 interrupt control register intc 594 tq0ccr0 tmq0 capture/compare register 0 timer 338 tq0ccr1 tmq0 capture/compare register 1 timer 340 appendix a register index preliminary user?s manual u17717ej2v0ud 729 (10/11) symbol name unit page tq0ccr2 tmq0 capture/compare register 2 timer 342 tq0ccr3 tmq0 capture/compare register 3 timer 344 tq0cnt tmq0 counter read buffer register timer 346 tq0ctl0 tmq0 control register 0 timer 331 tq0ctl1 tmq0 control register 1 timer 332 tq0ioc0 tmq0 i/o control register 0 timer 334 tq0ioc1 tmq0 i/o control register 1 timer 335 tq0ioc2 tmq0 i/o control register 2 timer 336 tq0opt0 tmq0 option register 0 timer 337 tq0ovic interrupt control register intc 594 tq1ccic0 interrupt control register intc 595 tq1ccic1 interrupt control register intc 595 tq1ccic2 interrupt control register intc 595 tq1ccic3 interrupt control register intc 595 tq1ccr0 tmq1 capture/compare register 0 timer 338 tq1ccr1 tmq1 capture/compare register 1 timer 340 tq1ccr2 tmq1 capture/compare register 2 timer 342 tq1ccr3 tmq1 capture/compare register 3 timer 344 tq1cnt tmq1 counter read buffer register timer 346 tq1ctl0 tmq1 control register 0 timer 331 tq1ctl1 tmq1 control register 1 timer 332 tq1ioc0 tmq1 i/o control register 0 timer 334 tq1ioc1 tmq1 i/o control register 1 timer 335 tq1ioc2 tmq1 i/o control register 2 timer 336 tq1opt0 tmq1 timer option register 0 timer 337 tq1ovic interrupt control register intc 595 tq2ccic0 interrupt control register intc 595 tq2ccic1 interrupt control register intc 595 tq2ccic2 interrupt control register intc 595 tq2ccic3 interrupt control register intc 595 tq2ccr0 tmq2 capture/compare register 0 timer 338 tq2ccr1 tmq2 capture/compare register 1 timer 340 tq2ccr2 tmq2 capture/compare register 2 timer 342 tq2ccr3 tmq2 capture/compare register 3 timer 344 tq2cnt tmq2 counter read buffer register timer 346 tq2ctl0 tmq2 i/o control register 0 timer 331 tq2ctl1 tmq2 i/o control register 1 timer 332 tq2ioc0 tmq2 i/o control register 0 timer 334 tq2ioc1 tmq2 i/o control register 1 timer 335 tq2ioc2 tmq2 i/o control register 2 timer 336 tq2opt0 tmq2 option register 0 timer 337 tq2ovic interrupt control register intc 595 ua0ctl0 uarta0 control register 0 uart 493 appendix a register index preliminary user?s manual u17717ej2v0ud 730 (11/11) symbol name unit page ua0ctl1 uarta0 control register 1 uart 515 ua0ctl2 uarta0 control register 2 uart 516 ua0opt0 uarta0 option control register 0 uart 495 ua0ric interrupt control register intc 594 ua0rx uarta0 receive data register uart 498 ua0str uarta0 status register uart 496 ua0tic interrupt control register intc 594 ua0tx uarta0 transmit data register uart 498 ua1ctl0 uarta1 control register 0 uart 493 ua1ctl1 uarta1 control register 1 uart 515 ua1ctl2 uarta1 control register 2 uart 516 ua1opt0 uarta1 option control register 0 uart 495 ua1ric interrupt control register intc 594 ua1rx uarta1 receive data register uart 498 ua1str uarta1 status register uart 496 ua1tic interrupt control register intc 594 ua1tx uarta1 transmit data register uart 498 ua2ctl0 uarta2 control register 0 uart 493 ua2ctl1 uarta2 control register 1 uart 515 ua2ctl2 uarta2 control register 2 uart 516 ua2opt0 uarta2 option control register 0 uart 495 ua2ric interrupt control register intc 595 ua2rx uarta2 receive data register uart 498 ua2str uarta2 status register uart 496 ua2tic interrupt control register intc 595 ua2tx uarta2 transmit data register uart 498 ua3ctl0 uarta3 control register 0 uart 493 ua3ctl1 uarta3 control register 1 uart 515 ua3ctl2 uarta3 control register 2 uart 516 ua3opt0 uarta3 option control register 0 uart 495 ua3ric interrupt control register intc 595 ua3rx uarta3 receive data register uart 498 ua3str uarta3 status register uart 496 ua3tic interrupt control register intc 595 ua3tx uarta3 transmit data register uart 498 vswc system wait control register cpu 84 wdte watchdog timer enable register wdt 455 wdtm2 watchdog timer mode register 2 wdt 453, 598 wtic interrupt control register intc 594 wtiic interrupt control register intc 594 wtm watch timer operation mode register wt 446 preliminary user?s manual u17717ej2v0ud 731 appendix b instruction set list b.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division resu lts and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list appendix b instruction set list preliminary user?s manual u17717ej2v0ud 732 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). appendix b instruction set list preliminary user?s manual u17717ej2v0ud 733 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition code (cccc) condition formula explanation 0 0 0 0 ov = 1 overflow 1 0 0 0 ov = 0 no overflow 0 0 0 1 cy = 1 carry lower (less than) 1 0 0 1 cy = 0 no carry not lower (greater than or equal) 0 0 1 0 z = 1 zero 1 0 1 0 z = 0 not zero 0 0 1 1 (cy or z) = 1 not higher (less than or equal) 1 0 1 1 (cy or z) = 0 higher (greater than) 0 1 0 0 s = 1 negative 1 1 0 0 s = 0 positive 0 1 0 1 ? always (unconditional) 1 1 0 1 sat = 1 saturated 0 1 1 0 (s xor ov) = 1 less than signed 1 1 1 0 (s xor ov) = 0 greater than or equal signed 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed 1 1 1 1 ((s xor ov) or z) = 0 greater than signed appendix b instruction set list preliminary user?s manual u17717ej2v0ud 734 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 4 4 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r appendix b instruction set list preliminary user?s manual u17717ej2v0ud 735 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11 appendix b instruction set list preliminary user?s manual u17717ej2v0ud 736 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3 appendix b instruction set list preliminary user?s manual u17717ej2v0ud 737 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 appendix b instruction set list preliminary user?s manual u17717ej2v0ud 738 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 appendix b instruction set list preliminary user?s manual u17717ej2v0ud 739 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). appendix b instruction set list preliminary user?s manual u17717ej2v0ud 740 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai p.r. china p.c:200120 tel: 021-5888-5400 http://www.cn.necel.com/ nec electronics hong kong ltd. 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886-9318 http://www.hk.necel.com/ seoul branch 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-2719-2377 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ for further information, please contact: g05.11-1a [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 164 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52180 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands limburglaan 5 5616 hr eindhoven the netherlands tel: 040 265 40 10 |
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